• Title/Summary/Keyword: Network Clock

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Federated Filter Approach for GNSS Network Processing

  • Chen, Xiaoming;Vollath, Ulrich;Landau, Herbert
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • v.1
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    • pp.171-174
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    • 2006
  • A large number of service providers in countries all over the world have established GNSS reference station networks in the last years and are using network software today to provide a correction stream to the user as a routine service. In current GNSS network processing, all the geometric related information such as ionospheric free carrier phase ambiguities from all stations and satellites, tropospheric effects, orbit errors, receiver and satellite clock errors are estimated in one centralized Kalman filter. Although this approach provides an optimal solution to the estimation problem, however, the processing time increases cubically with the number of reference stations in the network. Until now one single Personal Computer with Pentium 3.06 GHz CPU can only process data from a network consisting of no more than 50 stations in real time. In order to process data for larger networks in real time and to lower the computational load, a federated filter approach can be considered. The main benefit of this approach is that each local filter runs with reduced number of states and the computation time for the whole system increases only linearly with the number of local sensors, thus significantly reduces the computational load compared to the centralized filter approach. This paper presents the technical aspect and performance analysis of the federated filter approach. Test results show that for a network of 100 reference stations, with the centralized approach, the network processing including ionospheric modeling and network ambiguity fixing needs approximately 60 hours to process 24 hours network data in a 3.06 GHz computer, which means it is impossible to run this network in real time. With the federated filter approach, only less than 1 hour is needed, 66 times faster than the centralized filter approach. The availability and reliability of network processing remain at the same high level.

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Design and Implementation of PTP Gateway to Extend IEEE 1588 to Zigbee networks (IEEE 1588의 Zigbee 네트워크 확장을 위한 PTP 게이트웨이 설계 및 구현)

  • Cho, Hyun-Tae;Jung, Yeon-Su;Lee, Seung-Woo;Jin, Young-Woo;Baek, Yun-Ju
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.12A
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    • pp.971-981
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    • 2009
  • The coordination of distributed entities and events requires time synchronization. Precision time synchronization enables a variety of extensions of applications and provides much accurate information. The IEEE 1588 precision time protocol (PTP) provides a standard method to synchronize devices in a network. This paper deals with the design and implementation of a PTP gateway to extend IEEE 1588 to Zigbee networks. The PTP gateway can not only extend IEEE 1588 to Zigbee networks but also share the same time reference using IEEE 1588 between two or more Zigbee networks. This paper also presents experiments and performance evaluation of time synchronization using the PTP gateway. Our result established a method for nodes in a network to maintain their clocks to within a 300 nanosecond offset from the reference clock of a master node via Ethernet.

DEEP-South: Round-the-Clock Physical Characterization and Survey of Small Solar System Bodies in the Southern Sky

  • Moon, Hong-Kyu;Kim, Myung-Jin;Roh, Dong-Goo;Park, Jintae;Yim, Hong-Suh;Choi, Young-Jun;Bae, Young-Ho;Lee, Hee-Jae;Oh, Young-Seok
    • The Bulletin of The Korean Astronomical Society
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    • v.41 no.1
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    • pp.54.2-54.2
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    • 2016
  • Korea Microlensing Telescope Network (KMTNet) is the first optical survey system of its kind in a way that three KMTNet observatories are longitudinally well-separated, and thus have the benefit of 24-hour continuous monitoring of the southern sky. The wide-field and round-the-clock operation capabilities of this network facility are ideal for survey and the physical characterization of small Solar System bodies. We obtain their orbits, absolute magnitudes (H), three dimensional shape models, spin periods and spin states, activity levels based on the time-series broadband photometry. Their approximate surface mineralogy is also identified using colors and band slopes. The automated observation scheduler, the data pipeline, the dedicated computing facility, related research activity and the team members are collectively called 'DEEP-South' (DEep Ecliptic Patrol of Southern sky). DEEP-South observation is being made during the off-season for exoplanet search, yet part of the telescope time is shared in the period between when the Galactic bulge rises early in the morning and sets early in the evening. We present here the observation mode, strategy, software, test runs, early results, and the future plan of DEEP-South.

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A MAC System Design for High-speed UWB SoC (고속 UWB SoC의 MAC 시스템 설계)

  • Kim, Do-Hoon;Wee, Jeong-Wook;Lee, Chung-Yong
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.4
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    • pp.1-5
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    • 2011
  • We present the implementation of MAC system for MBOA UWB SoC. The implemented MBOA MAC algorithm is not master control mechanism, but distributed network mechanism. Therefore, mesh network can be easily constructed because MAC consists of distributed network and administrates network. The ARM926EJ with cache is adopted for high performnace and AMBA bus is applied for system design and reuse. In addition, the system operating clock management algorithm is implemented for low power consumption. The dedicated DMA for MAC is designed between the system memory buffer and MAC hardware, and the dedicated DMA for USB 2.0 is also implemented between system memory buffer and host for high data transaction.

On-chip Decoupling Capacitor for Power Integrity (전력 무결성을 위한 온 칩 디커플링 커패시터)

  • Cho, Seungbum;Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.24 no.3
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    • pp.1-6
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    • 2017
  • As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

Visual communications Over Broadband Packet Network (광대역 패킷 망에서의 영상통신)

  • 이상훈
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.14 no.5
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    • pp.521-530
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    • 1989
  • Broadband ATM(Asynchronous Transfer Mode) networking techniques based on lightwave technology and high speed integrated circuits appear to be the choice of transport technology for broadband ISDN. Among other problems, the issue of video transport over broadband packet(ATM) networks still requries further investigation. In this paper, the problems of transporting video signals over a broaband packet network are investigated together with possible solutions. In particular, clock recovery packet loss compensation and transport technique based on hierarchical video coding scheme are described in detail. This would allow efficient bandwidth sharing and minimum degradation in video quality.

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Design of High Speed Encryption/Decryption Hardware for Block Cipher ARIA (블록 암호 ARIA를 위한 고속 암호기/복호기 설계)

  • Ha, Seong-Ju;Lee, Chong-Ho
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.9
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    • pp.1652-1659
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    • 2008
  • With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.

The CDMA Mobile System Architecture

  • Shin, Sung-Moon;Lee, Hun;Han, Ki-Chul
    • ETRI Journal
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    • v.19 no.3
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    • pp.98-115
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    • 1997
  • The architecture of the CDMA mobile system (CMS) is developed based on three function groups - service resource, service control, and service management groups. In this paper, the CMS architecture is discussed from the point of view of implementing these functions. The variable length packets are used for transmission. The synchronization clock signals are derived form the GPS receiver. The open loop and closed loop techniques are used for the power control. The internationally accepted signaling and network protocols are employed. The call control for the primary services in designed to provide efficient mobile telecommunication services. The softer handoff is implemented in one card. The mobile assisted handoff and the network assisted handoff are employed in the soft and hard handoffs. The authentication is based on the secret data which includes random numbers. The management functions, which include the location management, resource management, cell boundary management and OAM management, are implemented to warrant the system efficiency, maximum capacity and high reliability. The architecture ensures that the CMS is flexible and expandable to provide subscribers with economic and efficient system configuration. The dynamic power control, adaptive channel allocation. and dynamic cell boundary management are recommended for future work.

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Effective Estimation Method of Routing Congestion at Floorplan Stage for 3D ICs

  • Ahn, Byung-Gyu;Kim, Jae-Hwan;Li, Wenrui;Chong, Jong-Wha
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.11 no.4
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    • pp.344-350
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    • 2011
  • Higher integrated density in 3D ICs also brings the difficulties of routing, which can cause the routing failure or re-design from beginning. Hence, precise congestion estimation at the early physical design stage such as floorplan is beneficial to reduce the total design time cost. In this paper, an effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage. This method uses synthesized virtual signal nets, power/ground network and clock network to achieve the estimation. During the synthesis, the TSV location is also under consideration. The experiments indicate that our proposed method had small difference with the estimation result got at the post-placement stage. Furthermore, the comparison of congestion maps obtained with our method and global router demonstrates that our estimation method is able to predict the congestion hot spots accurately.

The Study on Distribution Clock Synchronization of EtherCAT Communication System (이더캣 통신시스템에서 분산 클럭 동기화에 관한 연구)

  • Moon, Yongseomn;Vo, Trong Tuan Anh;Lee, Youngpil;Cha, Hyunrok
    • The Journal of the Korea institute of electronic communication sciences
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    • v.4 no.4
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    • pp.293-300
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    • 2009
  • In this paper, we describe a method for synchronization protocol method used in control system based on network and IEEE 1599 synchronization method which used for implementation of synchronization technology of advanced industrial Ethernet. We also implement and perform the experiment for synchronization technology of EtherCAT communication which is one of the industrial Ethernet technology used IEEE 1599 synchronization technology based on time. And we describe an evaluation for experiment result, improve the problem and future plan.

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