• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.44-54
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• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

• Journal of electromagnetic engineering and science
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• v.15 no.2
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• pp.76-81
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• 2015

This paper presents a design of a transmission line negative group delay (NGD) circuit with multiple pole characteristics. By inserting an additional transmission line into a conventional NGD circuit, the proposed circuit provides further design parameters to obtain wideband group delay (GD) and to help reduce signal attenuation. As a result, the number of gain compensating amplifiers can be reduced, which can contribute to stable operation when integrated into RF systems. The multiple pole characteristics can provide wider NGD bandwidth and can be obtained by connecting resonators with slightly different center frequencies separated by quarter-wavelength transmission lines. For experimental validation, an NGD circuit with two poles GD characteristic is designed, simulated, and measured.

• Journal of electromagnetic engineering and science
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• v.16 no.1
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• pp.7-12
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• 2016

This paper presents the design of a negative group delay circuit (NGDC) using the filter synthesis approach. The proposed design method is based on a frequency transformation from a low-pass filter (LPF) to a bandstop filter (BSF). The predefined negative group delay (NGD) can be obtained by inserting resistors into resonators. To implement a circuit with a distributed transmission line, a circuit conversion technique is employed. Both theoretical and experimental results are provided for validating of the proposed approach. For NGD bandwidth and magnitude flatness enhancements, two second-order NGDCs with slightly different center frequencies are cascaded. In the experiment, group delay of $5.9{\pm}0.5ns$ and insertion loss of $39.95{\pm}0.5dB$ are obtained in the frequency range of 1.935-2.001 GHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.374-379
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• 2010

In this paper, we have mathematically analyzed lumped element type negative group delay circuit (NGDC) and derived general design equation. The applicability of the proposed design equation is validated with mathematical and circuit simulation as well as with experimental results for intentional mobile telecommunication 2000 (IMT-2000) downlink band. As a design example, single branch NGDC with -0.8ns of group delay (GD) for narrow bandwidth of the specific frequency is simulated and fabricated. Finally, $\pi$-network NGDC is proposed and validated to obtain wideband GD response of $-1.7{\pm}0.06$ nsec for 60 MHz.

• Journal of electromagnetic engineering and science
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• v.19 no.1
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• pp.56-63
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• 2019

Typical negative group delay circuits (NGDC) are analyzed in terms of signal attenuation, group delay, and bandwidth using S-parameters. By inverting these formulations, we derive and present the design equations (for NGD circuit elements) for a desired specification of the two among the three parameters. The proposed design method is validated through simulation examples for narrow- and wide-band pulse inputs in the time and frequency domains. Moreover, an NGDC composed of lumped elements is fabricated at 1 GHz for measurement. As a function of frequency, the circuit-/EM-simulated and measured group delays are in good agreement. The provided simple NGDC design equations may be useful for many applications that require compensations of some signal delays.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.681-689
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• 2010

We will demonstrate a novel topology for the feedforward amplifier. This amplifier does not use a delay element thus providing an efficiency enhancement and a size reduction by employing a distributed element negative group delay circuit. The insertion loss of the delay element in the conventional feedforward amplifier seriously degrades the efficiency. Usually, a high power co-axial cable or a delay line filter is utilized for a low loss, but the insertion loss, cost and size of the delay element still acts as a bottleneck. The proposed negative group delay circuit removes the necessity of the delay element required for a broadband signal suppression loop. With the fabricated 2-stage distributed element negative group delay circuit with -9 ns of total group delay, a 0.2 dB of insertion loss, and a 30 MHz of bandwidth for a wideband code division multiple access downlink band, the feedforward amplifier with the proposed topology experimentally achieved a 19.4 % power added efficiency and a -53.2 dBc adjacent channel leakage ratio with a 44 dBm average output power.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.3
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• pp.236-244
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• 2010

In this paper, a planar structure negative group delay circuit(NGDC) is proposed to overcome the limited availability of the component values required for the prototype lumped element(LE) NGDC design. From the prototype LE circuit analysis, general design equations and the conditions to obtain the NGD are derived and illustrated. Then the LE circuit is converted into the planar structure by applying the transmission line resonator(TLR) theory. As a design example, the LE NGDC and the proposed planar structure NGDC are designed and compared. To estimate the commercial applicability, 2-stage reflection type planar NGDC with -5.6 ns of total group delay, -0.2 dB of insertion loss, and 30 MHz of bandwidth together with 0.1 dB and 0.5 ns of the magnitude and group delay flatness, respectively, for Wideband Code Division Multiple Access(WCDMA) downlink band is fabricated and demonstrated. Also, to show the applicability of the proposed NGDC, we have configured a simple signal cancellation loop and obtained good loop suppression performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.429-432
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• 2017

In this paper, a full - wave rectifying harvesting circuit with a high-performance comparator is designed. Designed circuits are divided into Negative Voltage Converter and Active Diode stages. The comparator included in the active diode stage is implemented as a 3-stage type and divided into pre-amplification, decision circuit, and output buffer stages. The main purpose of this comparator is to reduce the propagation delay and improve the voltage and power efficiency of the harvesting circuit. The proposed circuit is designed with magna $0.35{\mu}m$ CMOS process and its operation is verified by simulation. The chip area of the designed energy harvesting circuit is $900{\mu}m{\times}712{\mu}m$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1143-1153
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• 2010

In this paper, we propose an alternative method to increase the distortion cancellation bandwidth of an analog RF feedback power amplifier by using a negative group delay circuit(NGDC). A limited distortion cancellation bandwidth due to the group delay(GD) mismatch discouraged the use of feedback technique in spite of its powerful linearization performance. With the fabricated NGDC with positive phase slope over frequency, the feedback amplifier of the proposed topology experimentally achieved adjacent channel leakage ratio(ACLR) improvement of 15 dB over 50 MHz bandwidth at wideband code division multiple access(WCDMA) downlink band when tested with 2-carrier WCDMA signal. At an average output power of 28 dBm, ACLR of 25.1 dB is improved to obtain -53.2 dBc at 5 MHz offset.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.16-25
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• 1997

This paper shows a SDRAM opeating in 200MHz clock cycle which it use data interleave and pipelining for high speed operation. We proposed NdC (Negative DEaly circuit) to improve clock to access time(tAC) characteristics, also we proposed low power WL(wordline)driver circit and high efficiency VPP charge-pump circit. Our all circuits has been fabricated using 0.4um CMOS process, and the measured maximum speed is 200Mbytes/s in LvTTL interface.