• Title/Summary/Keyword: Negative voltage

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Droop Control to Compensate Load Voltage Unbalance for Inverter-based Distributed Generations with Unequal Impedance Lines (불균등 임피던스 선로를 갖는 인버터기반 분산전원의 부하전압 불평형을 보상하는 드룹 제어)

  • Yang, Won-Mo;Kim, Hyun-Jun;Han, Byung-Moon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.7
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    • pp.1193-1203
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    • 2016
  • This paper proposes a droop control scheme to compensate the unbalanced line-to-line voltage of unbalanced 3-phase load which is coupled with two inverter-based distributed generations through unequal impedance lines. Unbalanced line-to-line load voltages occur due to using single-phase loads, which brings about bad effects on the coupled inverters and the distributed generations. In order to compensate the unbalanced line-to-line voltages, a positive sequence voltage control was used for sharing the active and reactive power and a negative sequence control was used for reducing the negative sequence voltage. The feasibility of the proposed scheme was first verified by computer simulations, and then experiments with a hardware set-up built in the lab. The experimental results were compared with the simulation results to confirm the feasibility of the proposed scheme.

Effect of Negative Substrate Bias Voltage on the Microstructure and Mechanical Properties of Nanostructured Ti-Al-N-O Coatings Prepared by Cathodic Arc Evaporation

  • Heo, Sungbo;Kim, Wang Ryeol;Park, In-Wook
    • Journal of the Korean institute of surface engineering
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    • v.54 no.3
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    • pp.133-138
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    • 2021
  • Ternary Ti-X-N coatings, where X = Al, Si, Cr, O, etc., have been widely used for machining tools and cutting tools such as inserts, end-mills, and etc. Ti-Al-N-O coatings were deposited onto silicon wafer and WC-Co substrates by a cathodic arc evaporation (CAE) technique at various negative substrate bias voltages. In this study, the influence of substrate bias voltages during deposition on the microstructure and mechanical properties of Ti-Al-N-O coatings were systematically investigated to optimize the CAE deposition condition. Based on results from various analyses, the Ti-Al-N-O coatings prepared at substrate bias voltage of -80 V in the process exhibited excellent mechanical properties with a higher compressive residual stress. The Ti-Al-N-O (-80 V) coating exhibited the highest hardness around 30 GPa and elastic modulus around 303 GPa. The improvement of mechanical properties with optimized bias voltage of -80 V can be explained with the diminution of macroparticles, film densification and residual stress induced by ion bombardment effect. However, the increasing bias voltage above -80 V caused reduction in film deposition rate in the Ti-Al-N-O coatings due to re-sputtering and ion bombardment phenomenon.

A Syudy On DVR Control for Unbalanced Voltage Compensation (불평형 전압 보상을 위한 DVR 제어에 관한 연구)

  • Jung, Hong-Ju;Chung, Joon-Mo;Song, Jong-Whan
    • Proceedings of the KIEE Conference
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    • 2001.04a
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    • pp.218-221
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    • 2001
  • This paper presents a new control scheme for a Dynamic Voltage Restorer(DVR) system consisting of series voltage source PWM converters. The control system is designed using differential controllers and digital filters to transfer the faulted ac source voltage to a d-q model and to separate the positive and negative sequence component for individual compensation. The performance of the presented controller and scheme are confirmed through simulation and actual experiment.

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Analysis IGBT gate Surge voltage characterization by stray inductance (기생 인덕턴스에 의한 게이트 서지 전압 특성분석)

  • Lee, Gun Ho
    • Proceedings of the KIPE Conference
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    • 2014.07a
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    • pp.285-286
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    • 2014
  • Recently, the unipolar gate power source is preferred in inverter system because of cost reduction reason. In this case, designer uses 0V source for turning-off the switching devices instead of negative voltage at Vee source. If the gate driver circuit has some stray inductance, the gate voltage would happen a surge voltage. This paper analyzes that of stray inductance effect during the switching behavior in the circuit and the proposed solutions were verified by pulse test.

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A Low Noise Phase Locked Loop with Three Negative Feedback Loops (세 개의 부궤환 루프를 가진 저잡음 위상고정루프)

  • Young-Shig Choi
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.16 no.4
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    • pp.167-172
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    • 2023
  • A low-noise phase-locked loop(PLL) with three negative feedback loops has been proposed. It is not easy to improve noise characteristics with a conventional PLL. The added negative feedback loops reduce the input voltage magnitude of voltage controlled oscillator which determines the jitter characteristics, enabling the improvement of noise characteristics. Simulation results show that the jitter characteristics are improved as a negative feedback loop is added. In the case of power consumption, it slightly rises by about 10%, but jitter characteristics are improved by about two times. The proposed PLL was simulated with Hspice using a 1.8V 180nm CMOS process.

Output Voltage Regulation for Harmonic Compensation under Islanded Mode of Microgrid

  • Lim, Kyungbae;Choi, Jaeho
    • Journal of Power Electronics
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    • v.17 no.2
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    • pp.464-475
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    • 2017
  • This study examines a P+multi resonant-based voltage control for voltage harmonics compensation under the islanded mode of a microgrid. In islanded mode, the inverter is defined as a voltage source to supply the full local load demand without the connection to the grid. On the other hand, the output voltage waveform is distorted by the negative and zero sequence components and current harmonics due to the unbalanced and nonlinear loads. In this paper, the P+multi resonant controller is used to compensate for the voltage harmonics. The gain tuning method is assessed by the tendency analysis of the controller as the variation of gain. In addition, this study analyzes the slight voltage magnitude drop due to the practical form of the P+multi resonant and proposes a counter method to solve this problem by adding the PI-based voltage restoration method. The proposed P+multi resonant controller to compensate for the voltage harmonics is verified through the PSIM simulation and experimental results.

The New Design of CMOS Voltage-Current Reference Circuit for Stable Voltage-Current Applications (새로운 CMOS 전압-전류 안정화 회로 설계)

  • Kim, Yeong-Min;Hwang, Jong-Sun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07b
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    • pp.1239-1243
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    • 2004
  • A novel voltage-current reference circuit for stable voltage-current applications is Proposed. Circuits for a positive and for a negative voltage-current reference are presented and are designed with commercial CMOS technology. The voltage-current reference that is stable over ambient temperature variations is an important component of most data acquisition systems. These results are verified by the HSPICE simulation $0.8{\mu}m$ parameter. As the result, the temperature dependency of output voltage and output current each is $0.57mV/^{\circ}C$, $0.11{\mu}A/^{\circ}C$ and the power dissipation is 1.8 mV on 5V supply voltage.

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Deposition of diamond thin film by MPECVD method (마이크로웨이브 화학 기상 증착법을 이용한 다이아몬드 박막의 증착)

  • Sung Hoon Kim;Young Soo Park;Jo-Won Lee
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.4 no.1
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    • pp.92-99
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    • 1994
  • Diamond thin film was deposited on n type (100) Si substrate by MPECVD(Microwave plasma Enhanced Chemical Vapor Deposition). For the increase in nucleation density of diamond, Si substrate was pretreated by diamond powder or negative bias voltage was applied to the substrate during the initial deposition. In the case of retreated Si substrate, the diamond thin film quality was enhanced with increasing the total pressure in the range of 20~150 Torr. For the negative bias voltage, the formation condition of the diamond was seriously affected by $CH_4$ concentration and total pressure. The formation condition will be discussed with electrical current of substrate generated by plasma ions which depend on $CH_4$concentration, bias voltage, and total pressure.

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A Design of Differential Voltage Clamped VCO for Improved Characteristics of Operating Frequency (개선된 동작 주파수 특성을 갖는 차동 전압 클램프 VCO 설계)

  • Kim, D.G.;Oh, R.;Woo, Y.S.;Sung, Man-Y.
    • Proceedings of the KIEE Conference
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    • 2000.07d
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    • pp.3181-3183
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    • 2000
  • As the fact that the simple data of text and sound in early year have been changed to be high quality images and sounds. PLL(Phase-Locked Loop) system plays an important role in communication system. VCO(Voltage Controlled Oscillator) is the most important part in PLL system because it can have critical effects on operation of PLL. Recently, it has been raised the necessity of high speed and high accuracy circuit application. In this paper, a new differential voltage clamped VCO using negative-skewed path is suggested. Using a dual-delay scheme to implement the VCO, higher operation frequency and wider tuning are achieved simultaneously. The dual-delay scheme means that both the negative skewed delay paths and the normal delay paths exist in the same ring oscillator. The negative skewed delay paths decrease the unit delay time of the ring oscillator below the single inverter delay time. As a result, higher operation frequency can be obtained. The whole characteristics of VCO are simulated by using HSPICE. Simulation results show that the resulting operating frequencies are 50% higher than those obtainable from the conventional approaches.

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A Integrated Circuit Design of DC-DC Converter for Flat Panel Display (플랫 판넬표시장치용 DC-DC 컨버터 집적회로의 설계)

  • Lee, Jun-Sung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.10
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    • pp.231-238
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    • 2013
  • This paper describes a DC-DC converter IC for Flat Panel Displays. In case of operate LCD devices various type of DC supply voltage is needed. This device can convert DC voltage from 6~14[V] single supply to -5[V], 15[V], 23[V], and 3.3[V] DC supplies. In order to meet current and voltage specification considered different type of DC-DC converter circuits. In this work a negative charge pump DC-DC converter(-5V), a positive charge pump DC-DC converter(15V), a switching Type Boost DC-DC converter(23V) and a buck DC-DC converter(3.3V). And a oscillator, a thermal shut down circuit, level shift circuits, a bandgap reference circuits are designed. This device has been designed in a 0.35[${\mu}m$] triple-well, double poly, double metal 30[V] CMOS process. The designed circuit is simulated and this one chip product could be applicable for flat panel displays.