• Title/Summary/Keyword: Nano-CMOS

Search Result 113, Processing Time 0.029 seconds

Design and Fabrication of Micro-sensors Using CMOS Technology (CMOS 공정을 이용한 마이크로 센서의 설계 및 제작)

  • Lee, Sung-Pil;Lee, Ji-Gong;Chang, Choong-Won;Kim, Ju-Nam;Lee, Yong-Jae;Yang, Heung-Yol
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2007.11a
    • /
    • pp.347-348
    • /
    • 2007
  • On-chip micro humidity sensor, using $CN_x$ films for the sensing material, was designed, simulated, and fabricated with Op amp based readout circuit and diode temperature sensors. To compensate the temperature and other gases, two methods were applied. One is wheatstone-bridge with reference FET that eliminates other undesirable chemical species, and the other is a diode temperature sensor to compensate the temperature effect. $CN_x$ film can be a new humidity sensing material, and has a strong potential to adapt to smart sensors or multi-sensors using MEMS or nano-technology. A particular design technology for integration of sensors and systems together was proposed that whole fabrication process could be achieved by a standard CMOS process.

  • PDF

Design and Experiment of an Optical System using a Prism with a High Enough Refractive Index for Wet Fingerprint Identification (물 묻은 지문을 인식하기 위한 프리즘 광학계의 설계 및 실험적 고찰)

  • Kang, Myung-Hoon;Kim, Jin-Su;Jung, Jin-Woo;Ko, Eun-Mi;Kim, Jae-Gu;Cho, Guan-Sik;Song, Han-Jung;Hwang, Jae-Mun
    • Korean Journal of Optics and Photonics
    • /
    • v.18 no.6
    • /
    • pp.395-400
    • /
    • 2007
  • We propose a design and analysis of an optical system using a prism with a high enough refractive index for wet fingerprint identification. Important parameters including the tilting angle($\beta$) of the $1^{st}$ image plane, an anamorphic distortion, and a tilt of image plane are considered in terms of the apex angle of the prism($\alpha$) and refractive index of the prism material. Our suggestion on refractive index and apex angle of the prism corroborates well with experimental results.

Temperature Analysis of the Voltage Contolled Chaotic Circuit (전압 제어형 카오스회로의 온도특성 해석)

  • Park, Yongsu;Zhou, Jichao;Song, Hanjung
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.14 no.8
    • /
    • pp.3976-3982
    • /
    • 2013
  • This paper presents a temperature analysis of the chaotic behavior in the voltage controlled CMOS chaotic circuit. The circuit is based on a simple nonlinear function block which is needed for chaotic signal generation. It consists of a NFB (nonlinear function block), a level shifter and non-overlapping two-phase clock for sample and hold. By SPICE simulation, chaotic dynamics such as frequency spectra and bifurcations according to the temperature variations were analyzed. And, it was showed that the circuit can generate discrete chaotic signals within control voltage in the range from 1.2 V to 2.3 V in a specific temperature condition of $25^{\circ}C$.

Dependence on Dopant of Ni-silicide for Nano CMOS Device (Nano CMOS소자를 위한 Ni-silicide의 Dopant 의존성 분석)

  • 배미숙;지희환;이헌진;오순영;윤장근;황빈봉;왕진석;이희덕
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.40 no.11
    • /
    • pp.1-8
    • /
    • 2003
  • In this paper, the dependence of silicide properties such as sheet resistance and cross-sectional profile on the dopants for source/drain and gate has been characterized. There was little difference of sheet resistance among the dopants such as As, P, BF$_2$ and B$_{11}$ just a(ter formation of NiSi using RTP (Rapid Thermal Process). However, the silicide properties showed strong dependence on the dopants when thermal treatment was applied after silicidation. BF$_2$ implanted silicon showed the most stable property, while As implanted one showed the worst. The main reason of the excellent property of BF$_2$ sample is believed to be tile retardation of hi diffusion by the flourine. Therefore, retardation of Ni diffusion is highly desirable for high performance Ni-silicide technology.y.

Design of a PWM DC-DC Boost Converter IC for Mobile Phone Flash (휴대전화 플래시를 위한 PWM 전류모드 DC-DC converter 설계)

  • Jung, Jin-Woo;Heo, Yun-Seok;Park, Yong-Su;Kim, Nam-Tae;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.12 no.6
    • /
    • pp.2747-2753
    • /
    • 2011
  • In this paper, a PWM current-mode DC-DC boost converter for mobile phone flash application has been proposed. The converter which is operated with 5 Mhz high switching frequency is capable of reducing mounting area of passive devices such as inductor and capacitor, consequently is suitable for compact mobile phones. This boost converter consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. Meanwhile, the control block consists of pulse width modulator, error amplifier, oscillator etc. Proposed boost converter has been designed and verified in a $0.5\;{\mu}m$ 1-poly 2-metal CMOS process technology. Simulation results show that the output voltage is 4.26 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 Khz driven converter when the duty ratio is 0.15.

Mutually-Actuated-Nano-Electromechanical (MA-NEM) Memory Switches for Scalability Improvement

  • Lee, Ho Moon;Choi, Woo Young
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.17 no.2
    • /
    • pp.199-203
    • /
    • 2017
  • Mutually-actuated-nano-electromechanical (MA-NEM) memory switches are proposed for scalability improvement. While conventional NEM memory switches have fixed electrode lines, the proposed MA-NEM memory switches have mutually-actuated cantilever-like electrode lines. Thus, MA-NEM memory switches show smaller deformations of beams in switching. This unique feature of MA-NEM memory switches allows aggressive reduction of the beam length while maintaining nonvolatile property. Also, the scalability of MA-NEM memory switches is confirmed by using finite-element (FE) simulations. MA-NEM memory switches can be promising solutions for reconfigurable logic (RL) circuits.

A "Thru-Short-Open" De-embedding Method for Accurate On-Wafer RF Measurements of Nano-Scale MOSFETs

  • Kim, Ju-Young;Choi, Min-Kwon;Lee, Seong-Hearn
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.12 no.1
    • /
    • pp.53-58
    • /
    • 2012
  • A new on-wafer de-embedding method using thru, short and open patterns sequentially is proposed to eliminate the errors of conventional methods. This "thru-short-open" method is based on the removal of the coupling admittance between input and output interconnect dangling legs. The increase of the de-embedding effect of the lossy coupling capacitance on the cutoff frequency in MOSFETs is observed as the gate length is scaled down to 45 nm. This method will be very useful for accurate RF measurements of nano-scale MOSFETs.

Neural Interface with a Silicon Neural Probe in the Advancement of Microtechnology

  • Oh, Seung-Jae;Song, Jong-Keun;Kim, Sung-June
    • Biotechnology and Bioprocess Engineering:BBE
    • /
    • v.8 no.4
    • /
    • pp.252-256
    • /
    • 2003
  • In this paper we describe the status of a silicon-based microelectrode for neural recording and an advanced neural interface. We have developed a silicon neural probe, using a combination of plasma and wet etching techniques. This process enables the probe thickness to be controlled precisely. To enhance the CMOS compatibility in the fabrication process, we investigated the feasibility of the site material of the doped polycrystalline silicon with small grains of around 50 nm in size. This silicon electrode demonstrated a favorable performance with respect to impedance spectra, surface topography and acute neural recording. These results showed that the silicon neural probe can be used as an advanced microelectrode for neurological applications.

New RF Empirical Nonlinear Modeling for Nano-Scale Bulk MOSFET (나노 스케일 벌크 MOSFET을 위한 새로운 RF 엠피리컬 비선형 모델링)

  • Lee, Seong-Hearn
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.43 no.12 s.354
    • /
    • pp.33-39
    • /
    • 2006
  • An empirical nonlinear model with intrinsic nonlinear elements has been newly developed to predict the RF nonlinear characteristics of nano-scale bulk MOSFET accurately over the wide bias range. Using an extraction method suitable for nano-scale MOSFET, the bias-dependent data of intrinsic model parameters have been accurately obtained from measured S-parameters. The intrinsic nonlinear capacitance and drain current equations have been empirically obtained through 3-dimensional curve-fitting to their bias-dependent curves. The modeled S-parameters of 60nm MOSFET have good agreements with measured ones up to 20GHz in the wide bias range, verifying the accuracy of the nano-scale MOSFET model.

Electrical Characteristics of Si-O Superlattice Diode (Si-O 초격자 다이오드의 전기적 특성)

  • Park, Sung-Woo;Seo, Yong-Jin;Jeong, So-Young;Park, Chang-Jun;Kim, Ki-Wook;Kim, Sang-Yong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2002.11a
    • /
    • pp.175-177
    • /
    • 2002
  • Electrical characteristics of the Si-O superlattice diode as a function of annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy (MBE) system. Consequently, the experimental results of superlattice diode with multilayer Si-O structure showed the stable and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronic and quantum device as well as for the replacement of silicon-on-insulator (SOI) in ultra high speed and lower power CMOS devices in the future, and it can be readily integrated with silicon ULSI processing.

  • PDF