DOI QR코드

DOI QR Code

Temperature Analysis of the Voltage Contolled Chaotic Circuit

전압 제어형 카오스회로의 온도특성 해석

  • Park, Yongsu (Department of Electronics Engineering Chung Cheong University) ;
  • Zhou, Jichao (Department of Nano Systems Engineering Inje University) ;
  • Song, Hanjung (Department of Nano Systems Engineering Inje University)
  • 박용수 (충청대학교 전기전자학부) ;
  • 주계초 (인제대학교 나노시스템 공학부) ;
  • 송한정 (인제대학교 나노시스템 공학부)
  • Received : 2013.04.23
  • Accepted : 2013.08.07
  • Published : 2013.08.31

Abstract

This paper presents a temperature analysis of the chaotic behavior in the voltage controlled CMOS chaotic circuit. The circuit is based on a simple nonlinear function block which is needed for chaotic signal generation. It consists of a NFB (nonlinear function block), a level shifter and non-overlapping two-phase clock for sample and hold. By SPICE simulation, chaotic dynamics such as frequency spectra and bifurcations according to the temperature variations were analyzed. And, it was showed that the circuit can generate discrete chaotic signals within control voltage in the range from 1.2 V to 2.3 V in a specific temperature condition of $25^{\circ}C$.

본 논문에서는 전압 제어형 카오스 신호 발생회로를 설계하고, 온도변화에 따른 특성을 해석 하였다. 제안하는 CMOS 회로로 이루어지며, 카오스 특성의 전압 제어형 오실레이터의 온도 변화에 따른 특성해석을 실시하였다. 제안하는 회로는 2상 클럭의 샘플앤드회로 3개의 MOS 소자로 이루어지는 비선형 함수 블록과 소스 팔로워로 이루어지는 레벨 쉬프터로 구성된다. SPICE 모의실험을 통하여 온도변화에 따른, 비선형함수의 전달함수 변화를 통하여, 분기도 특성, 주파수 특성 등의 카오스 다이나믹스가 변화됨변화됨을 확인 하였다. 또한 $25^{\circ}C$ 의 온도 조건에서, 제어전압 1.2 V-2.3 V 범위에서, 카오스 신호가 생성됨을 확인하였다.

Keywords

References

  1. J. W. Jung, J. W. Lee and H. J. Song, "Implementation of an integrated op-amp based chaotic neuron model and observation of its chaotic dynamics," Chaos, vol.21 no.1, pp. 013105(1-7), March 2011 DOI: http://dx.doi.org/10.1063/1.3548064
  2. W. Kinzel, A. Englert and I. Kanter, "On chaos synchronization and secure communication," Phil. Trans. R. Soc, A , vol. 368 pp. 379-389 2010 DOI: http://dx.doi.org/10.1098/rsta.2009.0230
  3. X, Y. WANG and X. L. REN, "Chaotic synchronization of two electrical coupled neurons with unknown parameters based on adaptive control," Chin. Phys. Lett. vol. 28, no. 5, pp.050502(1-4), May 2011 DOI: http://dx.doi.org/10.1088/0256-307X/28/5/050502
  4. K. Aihara, T. Takbe, and M. Toyoda, "Chaotic neural networks," Phys. Lett. A, vol.144, no.6, pp.333-340, 1990. DOI: http://dx.doi.org/10.1016/0375-9601(90)90136-C
  5. Louis M. Pecora and Thomas L. Carroll, "Synchronization in chaotic systems," Phys. Rev. Lett. vol. 64, Feb, 1990. DOI: http://dx.doi.org/10.1103/PhysRevLett.64.821
  6. H. J. Song and K.D. Kwack, "CMOS circuit design and implementation of the discrete time chaotic chip", ISCAS 2002, vol. III, pp.73-74, 2002 DOI: http://dx.doi.org/10.1109/ISCAS.2002.1010163
  7. P. Dudek and V. D. Juncu, "Compact discrete-time chaos generator circuit", Electronics Letters, vol. 39, pp.1431-1432, 2003. DOI: http://dx.doi.org/10.1049/el:20030881
  8. M. Delgado-Restituto, A. Rodriguez-Vazquez, "Integrated chaos generators," Proceedings of the IEEE, vol. 90, pp. 747-767, May 2002. DOI: http://dx.doi.org/10.1109/JPROC.2002.1015005
  9. Jose L. Rossello, et al., "A simple CMOS chaotic integrated circuit," IEICE Electronics Express, vol. 5, no. 24, pp. 1042-1048, December 2008. DOI: http://dx.doi.org/10.1587/elex.5.1042
  10. S. Govindarajulu and T. J. Prasad, "Temperature variation insensitive energy efficient CMOS circuits design in 65 nm technology," International Journal of Engineering Science and Technology, vol. 2, no. 6, pp. 2140-2147, June 2010.