• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2013년도 춘계학술대회 논문집
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• pp.97-97
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• 2013

We present a comprehensive study on the integration of h-BN with silicon MOSFET. Temperature dependent mobility modeling is used to discern the effects of top-gate dielectric on carrier transport and identify limiting factors of the system. The result indicates that coulomb scattering and surface roughness scattering are the dominant scattering mechanisms for silicon MOSFETs at relatively low temperature. Interposing a layer of h-BN between $SiO_2$ and Si effectively weakens coulomb scattering by separating carriers in the silicon inversion layer from the charged centers as 2-dimensional h-BN is relatively inert and is expected to be free of dangling bonds or surface charge traps owing to the strong, in-plane, ionic bonding of the planar hexagonal lattice structure, thus leading to a significant improvement in mobility relative to undecorated system. Furthermore, the atomically planar surface of h-BN also suppresses surface roughness scattering in this Si MOSFET system, resulting in a monotonously increasing mobility curve along with gate voltage, which is different from the traditional one with a extremum in a certain voltage. Alternatively, high-k dielectrics can lead to enhanced transport properties through dielectric screening. Modeling indicates that we can achieve even higher mobility by using h-BN decorated $HfO_2$ as gate dielectric in silicon MOSFETs instead of h-BN decorated $SiO_2$.

• 한국전기전자재료학회논문지
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• 제18권12호
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• pp.1069-1074
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• 2005

In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.

• 센서학회지
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• 제15권1호
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• pp.1-6
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• 2006

We fabricated Si nano-wire MOSFET by using the conventional photolithography with a $1.5{\mu}m$ resolution. Si nano-wire was fabricated by using reactive ion etching (RIE), anisotropic wet etching and thermal oxidation on a silicon-on-insulator (SOI) substrate, and its width is 30 nm. Logarithmic circuit consisting of a NMOSFET and Si nano-wire MOSFET has been constructed for application to high-sensitivity image sensor. Its sensitivity was 1.12 mV/lux. The output voltage swing was 1.386 V.

• Transactions on Electrical and Electronic Materials
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• 제5권5호
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• pp.194-198
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• 2004

The influences of the deep-level concentration of p-type Si substrates on the optical properties of nano-porous silicon (PS) are investigated by deep level transient spectroscopy (DLTS) and photoluminescence (PL). Utilizing a Si substrate with Fe contaminations significantly enhanced the PL intensity of PS. All the PS samples formed on Fe-contaminated silicon substrates had stronger PL yield than that of reference PS without any intentional Fe contamination but the emission peak is not significantly changed. For the PS 1000 sample with Fe contamination of 1,000 ppb, the maximum PL intensity showed about ten times stronger PL than that of the reference PS sample. From PL and DLTS results, the PL efficiency strongly depends on the Fe-related trap concentration in Si substrates.

• Transactions on Electrical and Electronic Materials
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• 제4권6호
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• pp.32-37
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• 2003

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

• 소성∙가공
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• 제12권7호
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• pp.623-630
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• 2003

Nanomachining process, static nanoplowing, is one of the most promising lithographic technologies in terms of the low cost of operation and variety of workable materials. In nanomachining process, chemical effects are more dominant factor compared with those by physical deformation or fracture. For example, during the nanoscratch on a silicon surface in the atmosphere, micro protuberances are formed due to the mechanochemical reaction between diamond tip and the surfaces. On the contrary, in case of chemically stable materials, such as ceramic or glass, surface protuberances are not formed. The purpose of this study is to understand effects of the mechanochemical reaction between tip and surfaces on deformation behaviors of hard-brittle materials. Nanometerscale elasoplastic deformation behavior of single crystal silicon (100) was characterized with micro protuberance phenomena, and compared with that of borosilicate (Pyrex glass 7740). In addition, effects of the silicon protuberances on nanoscratch test results were discussed.

• 대한기계학회논문집A
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• 제30권10호
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• pp.1314-1319
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• 2006

This paper describes the novel fabrication method of the high-aspect-ratio nano structure which is impossible by conventional method using a shadow mask and a Deep X-ray Lithography (DXRL). The shadow mask with $1{\mu}m-sized$ apertures is fabricated on the silicon membrane using a conventional UV-lithography. The size of aperture is reduced to 200nm by accumulated low stress silicon nitride using a LPCVD (low pressure chemical vapor deposition) process. The X-ray mask is fabricated by depositing absorber layer (Au, $3{\mu}m$) on the back side of nano shadow mask. The thickness of an absorber layer must deposit dozens micrometers to obtain contrast more than 100 for a conventional DXRL process. The thickness of $3{\mu}m-absorber$ layer can get sufficient contrast using a central beam stop method, blocking high energy X-rays. The nano circle and nano line, 200nm in diameter in width, respectively, were demonstrated 700nm in height with a negative photoresist of SU-8.

• Korean Chemical Engineering Research
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• 제54권4호
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• pp.459-464
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• 2016

본 연구에서는 리튬이온 전지용 실리콘 음극소재의 사이클 안정성 및 율속 특성 향상을 위해 다공성 실리콘/탄소 복합소재의 전기화학적 특성을 조사하였다. 나노 실리카 제조는 스토버 방법을 사용하고 교반 속도, 교반 온도 및 $NH_3$/TEOS 비율을 조절 하여 100~500 nm 크기의 구형 실리카를 합성하였다. 구형 나노 실리카의 마그네슘 열환원과 산처리 과정을 통해 다공성 실리콘을 얻고, 제조된 다공성 실리콘에 Phenolic resin을 탄소전구체로 사용하여 최종적으로 다공성 실리콘/탄소 활물질을 합성하였다. 또한 $LiPF_6$ (EC:DMC:EMC=1:1:1 vol%) 전해액에서 다공성 실리콘/탄소 음극소재의 충 방전, 순환전압 전류, 임피던스 테스트 등의 전기화학적 특성을 조사 하였다. 다공성 실리콘/탄소 복합소재의 음극활물질로서 코인 전지의 성능을 조사한 결과 초기용량 및 40사이클 용량 보존율은 각각 2,006 mAh/g, 55.4%를 나타내었다.

• International Journal of Internet, Broadcasting and Communication
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• 제7권2호
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• pp.161-167
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• 2015

The performance of high power LEDs highly depends on the junction temperature. Operating at high junction temperature causes elevation of the overall thermal resistance which causes degradation of light intensity and lifetime. Thus, appropriate thermal management is critical for LED packaging. The main goal of this research is to improve thermal resistance by optimizing and comparing nano-pore silicon-based thermal substrate to insulated metal substrate and direct bonded copper thermal substrate. The thermal resistance of the packages are evaluated using computation fluid dynamic approach for 1 W single chip LED module.

• Macromolecular Research
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• 제16권4호
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• pp.353-359
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• 2008

Spheres of silicon resins with different compositions were prepared in one-step reaction from mixtures of water and water-insoluble precursors of polysiloxanes (PSO) and polysilsesquioxanes (PSQ) using different amines as catalysts. The presence of PSO and PSQ in the spheres was confirmed by their mechanical properties and FTIR spectroscopy. Spheres of pure PSO were obtained from only dimethoxymethylvinylsiloxane (DMMVS) and 3-mercaptopropylmethyldimethoxysilan (MPMDMS) when the reaction was induced with appropriate catalysts. DMMVS and MPMDMS always gave the most promising results regarding the formation of discrete solid spheres with the minimum tendency to form monolithic solids or fluid-like, premature products. The spheres were characterized by optical microscopy, scanning electron microscopy (SEM), and Fourier transform infrared (FTIR) spectroscopy. The mixtures containing larger amounts of PSO precursors commonly gave lower yields and softer spheres.