• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.199-202
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• 2004

NFGM(Nano-Floating Gate Memory) is a very prospective candidate memory for the next generation with MRAM, PRAM, PoRAM. Among these memory devices for the next generation, NFGM has a lot of merits such as a simple low cost fabrication process, improved retention time, lower operating voltages, high speed program/erase time and so on. Therefore, many intensive researches for NFGM have been performed to improve device performance and reliability, which depends on the ability to control particle size, size distribution, crystallity, areal particle density and tunneling oxide quality. In this paper, we investigate the researches for NFGM up to recently.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1494-1495
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• 2009

Thin Film Transistor(TFT) having CIS (CuInSe) semiconductor layer was fabricated and characterized. Heavily doped Si was used as a common gate electrode and PECVD Silicon nitride ($SiN_x$) was used as a gate dielectric material for the TFT. Source and drain electrodes were deposited on the $SiN_x$ layer and CIS layer was formed by a direct patterning method between source and drain electrodes. Nanoparticle of CIS material was used as the ink of the direct patterning method.

• Vacuum Magazine
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• v.2 no.2
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• pp.17-23
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• 2015

Medium Energy Ion Scattering (MEIS) has been successfully used for ultrathin film analysis such as gate oxides and multilayers due to its single atomic depth resolution in compostional and structural depth profiling. Recently, we developed a time-of-flight (TOF) MEIS for the first time, which can analyze a $10{\mu}m$ small spot. Small spot analysis would be useful for test pattern analysis in semiconductor industry and various thin film technology. The ion beam damage problem is minimized due to its improved collection efficiency by orders of magnitude and the ion beam neutralization problem is removed completely for quantitative analysis. Newly developed TOF-MEIS has been applied for gate oxides, ultra shallow junctions, nanoparticles, FINFET structures to provide compositional and structural profiles. Further development for submicron spot analysis and applications for functional nano thin films and nanostructured materials are expected for various nanotechnology and biotehnology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.107-108
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• 2005

Au and $Au/SiO_2$ nanoparticles(NPs) were synthesized by the colloidal method. The formation of Au and $Au/SiO_2$ NPs was confirmed using high resolution transmission electron microscopy (HRTEM). Synthesized solutions were deposited on Si wafer. The electrical properties of structures were measured using a semiconductor analyzer and a LCR meter. Capacitance versus voltage hysterisis curves showed the charge storage effect by Au and $Au/SiO_2$ NPs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.130-131
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• 2006

차세대 반도체 정보기억장치로서 활발하게 연구되고 있는 나노 부유 게이트 메모리 (Nano Floating Gate Memory) 소자를 위해 필수적인 요소인 나노 크리스탈의 형성을 위하여 다양한 굴절률을 가진 실리콘 질화막 (SiNx)을 형성하고 고온 열처리 (rapid thermal annealing)를 실시하여 나노 크리스탈의 형성과 특성에 대한 연구를 진행하였다. 다양한 굴절률을 가진 실리콘 질화막을 형성한 후 나노 크리스탈의 형성을 위하여 열처리를 수행하였고, photoluminescence (PL)를 통하여 굴절률이 높은 Si-rich SiNx 박막의 고온 열처리를 수행한 실리콘 질화막으로부터 나노 크리스탈의 형성을 확인할 수 있었다. 또한 열처리한 실리콘 질화막 위에 Al을 증착하여 MIS 구조를 형성한 후 Capacitance-Voltage (C-V) 특성을 측정하였으며, $900^{\circ}C$에서 열처리한 박막에서 나노 크리스탈에 의한 메모리 효과를 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.3
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• pp.162-168
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• 2006

To fabricate nanometer scale InGaAs HEMTs, we have successfully developed various novel nano-patterning techniques, including sidewall-gate process and e-beam resist flowing method. The sidewall-gate process was developed to lessen the final line length, by means of the sequential procedure of dielectric re-deposition and etch-back. The e-beam resist flowing was effective to obtain fine line length, simply by applying thermal excitation to the semiconductor so that the achievable final line could be reduced by the dimension of the laterally migrated e-beam resist profile. Applying these methods to the device fabrication, we were able to succeed in making 30nm $In_{0.7}Ga_{0.3}As$ HEMTs with excellent $f_T$ of 426GHz. Based on nanometer scale InGaAs HEMT technology, several high performance millimeter-wave integrated circuits have been successfully fabricated, including 77GHz MMIC chipsets for automotive radar application.

• Proceedings of the Korean Vacuum Society Conference
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• 2007.02a
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• pp.133-133
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• 2007

• Proceedings of the Korean Vacuum Society Conference
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• 2008.02a
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• pp.311-311
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• 2008

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.773-776
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• 2003

In this paper, we have designed the p-type SiGe MOSFET and analyzed the electrical characteristics. When the gate voltage is biased to -1.5V, the threshold voltage values are -0.97V and -1.15V at room temperature and 77K, respectively. We know that the operating characteristics of SiGe MOSFET is superior to the basic Si MOSFET which the threshold voltage is -1.36V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.356-357
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• 2008

The effects of $O_2$ plasma ashing process for surface treatment of nano-wire Bio-FET were investigated. In order to evaluate the plasma damage introduced by $O_2$ plasma ashing, a back-gate biasing method was developed and the electrical characteristics as a function of $O_2$ plasma power were measured. Serious degradations of electrical characteristics of nano-wire Bio-FET were observed when the plasma power is higher than 50 W. For curing the plasma damages, a forming gas anneal (2 %, $H_2/N_2$) was carried out at $400^{\circ}C$. As a result, the electrical characteristics of nano-wire Bio-FET were considerably recovered.