• Proceedings of the Korean Magnestics Society Conference
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• 2004.12a
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• pp.171-172
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• 2004

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05a
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• pp.86-89
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• 2004

Organic thin film transistors (OTFTs) are fabricated on the plastic substrate through 4-level mask process without photolithographic patterning to yield the simple fabrication process. And we herewith report for the effect of dielectric surface modification on the electrical characteristics of OTFTs. The KIST-JM-1 as an organic molecule for the surface modification is deposited onto the surface of zirconium oxide $(ZrO_2)$ gate dielectric layer. In this work, we have examined the dependence of electrical performance on the interface surface state of gate dielectric/pentacene, which may be modified by chemical properties in the gate dielectric surface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.413-413
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• 2009

Silicon nanowires (Si NWs)-based top-gate field-effect transistors (FETs) are constructed by using Si NWs transferred onto flexible plastic substrates. Si NWs are obtained from the silicon wafers using photolithography and anisotropic etching process, and transferred onto flexible plastic substrates. To evaluate the electrical performance of the silicon nanowires, we examined the output and transfer characteristics of a top-gate field-effect transistor with a channel composed of a silicon nanowire selected from the nanowires on the plastic substrate. From these FETs, a field-effect mobility and transconductance are evaluated to be $47\;cm^2/Vs$ and 272 nS, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.307.2-307.2
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• 2016

In this study, we synthesized Au nanoparticles (AuNPs) in polyacrylonitrile (PAN) thin films using a simple annealing process in the solid phase. The synthetic conditions were systematically controlled and optimized by varying the concentration of the Au salt solution and the annealing temperature. X-ray photoelectron spectroscopy (XPS) confirmed their chemical state, and transmission electron microscopy (TEM) verified the successful synthesis, size, and density of AuNPs. Au nanoparticles were generated from the thermal decomposition of the Au salt and stabilized during the cyclization of the PAN matrix. For actual device applications, previous synthetic techniques have required the synthesis of AuNPs in a liquid phase and an additional process to form the thin film layer, such as spin-coating, dip-coating, Langmuir-Blodgett, or high vacuum deposition. In contrast, our one-step synthesis could produce gold nanoparticles from the Au salt contained in a solid matrix with an easy heat treatment. The PAN:AuNPs composite was used as the charge trap layer of an organic nano-floating gate memory (ONFGM). The memory devices exhibited a high on/off ratio (over $10^6$), large hysteresis windows (76.7 V), and a stable endurance performance (>3000 cycles), indicating that our stabilized PAN:AuNPs composite film is a potential charge trap medium for next generation organic nano-floating gate memory transistors.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.317-318
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• 2012

현재의 반도체 산업에서 Hafnium oxide와 Hafnium silicates같은 high-k 물질은 CMOS gate와 DRAM capacitor dielectrics로 사용하기 위한 대표적인 물질에 속한다. MOSFET (metal oxide semiconductor field effect transistor)구조에서 gate length는 16 nm 이하로 계속 미세화가 연구 중이고, 또한 gate는 기존구조에서 Multi-gate구조로 다변화가 일어나고 있다. 이를 통해 게이트 절연막은 그 구조와 활용범위가 다양해지게 될 것이다. 동시에 leakage current와 dielectric break-down을 감소시키는 연구가 중요해지고 있다. 그러나 나노 영역에서의 기계적 특성에 대한 연구는 전무한 상태이다. 따라서 복잡한 회로 공정, 다양한 Multi-gate 구조, 신뢰도의 향상을 위해서는 유전박막 물질자체와 계면에서의 물리적, 기계적인 특징의 측정이 상당히 중요해지고 있다. 이에 본 연구는 Nano-indenter의 통해 경도(Hardness)와 탄성계수(Elastic modulus) 등의 측정을 통하여 시료 표면의 나노영역에서의 기계적 특성을 연구하고자 하였다. $HfO_2$게이트 절연막은 rf magnetron sputter를 이용해 Si (silicon) (100)기판위에 박막형태로 증착하였고, 이후 furnace에서 질소분위기로 온도(400, 450, $500^{\circ}C$)를 달리하여 20분 열처리를 하였다. 또한 Weibull distribution을 이용해 박막의 characteristic value를 계산하였으며, 실험결과 열처리 온도가 $400^{\circ}C$에서 $500^{\circ}C$로 증가함에 따라 경도와 탄성계수는 7.4 GPa에서 10.65 GPa으로 120.25 GPa에서 137.95 GPa으로 각각 증가하였다. 이는 재료적 측면으로 재료의 구조적 우수성이 증가된 것으로 판단된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.541-546
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• 2008

In this paper, conduction phenomena have been considered for nano structure double gate MOSFET, using the analytical model. The Possion equation is used to analytical model. The conduction mechanisms to have an influence on current conduction are thermionic emission and tunneling current, and subthreshold swings of this paper are compared with those of two dimensional simulation to verify this model. The deviation of current path and the influence of current path on subthreshold swing have been considered according to the dimensional parameters of double gate MOSFET, i.e. gate length, gate oxide thickness, channel thickness. The optimum channel doping concentration is determined as the deviation of conduction path is considered according doping concentration.

• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.359-365
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• 2007

In this paper we present a bottom-gate type of zinc oxide (ZnO) and Gallium (Ga) doped zinc oxide (GZO) based thin film transistors (TFTs) through applying a radio frequency (RF) magnetron sputtering method at room temperature. The gate leakage current can be reduced up to several ph by applying $SiO_2$ thermally grown instead of using new gate oxide materials. The root mean square (RMS) values of the ZnO and GZO film surface were measured as 1.07 nm and 1.65 nm, respectively. Also, the transmittances of the ZnO and GZO film were more than 80% and 75%, respectively, and they were changed as their film thickness. The ZnO and GZO film had a wurtzite structure that was arranged well as a (002) orientation. The ZnO TFT had a threshold voltage of 2.5 V, a field effect mobility of $0.027\;cm^2/(V{\cdot}s)$, a on/off ratio of $10^4$, a gate voltage swing of 17 V/decade and it operated in a enhancement mode. In case of the GZO TFT, it operated in a depletion mode with a threshold voltage of -3.4 V, a field effect mobility of $0.023\;cm^2/(V{\cdot}s)$, a on/off ratio of $2{\times}10^4$ and a gate voltage swing of 3.3 V/decade. We successfully demonstrated that the TFTs with the enhancement and depletion mode type can be fabricated by using pure ZnO and 1wt% Ga-doped ZnO.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.804-810
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• 2005

An analytical subthreshold swing (SS) model has been presented for double gate MOSFET(DGMOSFET) in this study. The results calculated by this model are more precise for about 10nm channel length and thickness than those derived from the previous models. The results of this model are compared with Medici simulation to varify the validity of this model, and good agreementes have been obtained. The changes of SS have been investigated for various channel lengths, channel thicknesses and gate oxide thicknesses using this model, given that these parameters are very important in design of DGMOSFET. This demonstrates that the proposed model provides useful data for design of nano-scale DGMOSFET. It is Known that the SS is improved to smaller ratios of channel thickness vs channel length and is smaller in very thin oxides. New gate dielectric materials with high permittivity have to be developed to enable design of nano-scale DGMOSFET.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.578-578
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• 2012

Graphene, a flat one-atom-thick two-dimensional layer of carbon atoms, is considered to be a promising candidate for nanoelectronics due to its exceptional electronic properties. Most of all, future nanoelectronics such as flexible displays and artificial electronic skins require low cost manufacturing process on flexible substrate to be integrated with high resolutions on large area. The solution based printing process can be applicable on plastic substrate at low temperature and also adequate for fabrication of electronics on large-area. The combination of printed electronics and graphene has allowed for the development of a variety of flexible electronic devices. As the first step of the study, we prepared the gate electrodes by printing onto the gate dielectric layer on PET substrate. We showed the performance of graphene field-effect transistor with electrohydrodynamic (EHD) inkjet-printed Ag gate electrodes.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.4
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• pp.325-327
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• 2011

In this paper, nonvolatile nano-floating gate memory devices are fabricated with ZnO nanowires and Al nanoparticles on a $SiO_2/Si$ substrate. Al nanoparticles used as floating gate nodes are formed by the sputtering method. The fabricated device exhibits a threshold voltage shift of -1.5 V. In addition, we investigate the endurance and retention characteristics of the nano-floating gate memory device.