• 한국전기전자재료학회논문지
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• 제18권12호
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• pp.1069-1074
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• 2005

In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1226-1227
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• 2008

In this study, a single p-type Si nanowire - Au nanoparticles nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of p-type Si nanowire-based field effect transistor (FET) devices with Au nanoparticles embedded in the $Al_2O_3$ gate materials and without the Au nanoparticles. Drain current versus gate voltage ($I_{DS}-V_{GS}$) characteristics of a single p-type Si nanowire - Au nanoparticle NFGM device show counterclockwise hysteresis loops with the threshold voltage shift of ${\Delta}V_{th}$= 3.0 V. However, p-type Si nanowire based top-gate device without Au nanoparticles does not exhibit a threshold voltage shift. This behavior is ascribed to the presence of the Au nanoparticles, and is indicative of the trapping and emission of electrons in the Au nanoparticles.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.354-355
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• 2008

The sensitivity and sensing margin of SOI(silicon on insulator) nano-wire BioFET(field effect transistor) were investigated by using back-gate bias. The channel conductance modulation was affected by doping concentration, channel length and channel width. In order to obtain high sensitivity and large sensing margin, low doping concentration, long channel and narrow width are required. We confirmed that the electrical sensing by back-gate bias is effective method for evaluation and optimization of bio-sensor.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.120-121
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• 2007

Nano-floating gate memory (NFGM) devices were fabricated by using the low temperature poly-Si thin films crystallized by ELA and the $In_2O_3$ nano-particles embedded in polyimide layers as charge storage. Memory effect due to the charging effects of $In_2O_3$ nano-particles in polyimide layer was observed from the TFT NFGM. The post-annealing in 3% diluted hydrogen $(H_2/N_2)$ ambient improved the retention characteristics of $In_2O_3$ nano-particles embedded poly-Si TFT NFGM by reducing the interfacial states as well as grain boundary trapping states.

• 대한전자공학회논문지SD
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• 제41권11호
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• pp.1-6
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• 2004

RFIC를 위한 Nanoscale MOSFET에서의 유효 게이트 저항을 직접 추출법으로 추출하여 다양한 게이트 길이에 대해 분석하였다. 추출된 유효 게이트 저항은 비교적 정확하면서 간소화된 모델을 통한 측정결과와 비교하여 10GHz 대역까지 잘 일치함을 확인하였다. 같은 공정기술로 제작된 소자들 중에서 reverse short channel 효과가 생기지 않는 긴 채널 MOSFET 소자의 경우에 일반적인 유효 게이트 저항에서와는 다른 인가전압 및 주파수 종속성을 가짐을 확인하였다. 특히, 문턱전압을 전후하여 주파수에 따라 상이한 결과를 나타내고 있으며, 게이트 인가전압이 문턱전압에 가까울 때 비이상적으로 큰 유효 게이트 저항값을 나타내었다. 이러한 특성은 직접추출법을 사용하는 RF MOSFET 모델링에 있어서 참고해야 할 중요한 특성이 될 것이다.

• Journal of Electrical Engineering and Technology
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• 제4권1호
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• pp.118-122
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• 2009

Organic thin film transistors with a pentacene active layer and various polymer gate insulators were fabricated and their performances were investigated. Characteristics of pentacene thin film transistors on different polymer substrates were investigated using an atomic force microscope (AFM) and x-ray diffraction (XRD). The pentacene thin films were deposited by thermal evaporation on the gate insulators of various polymers. Hexamethyldisilazane (HMDS), polyvinyl acetate (PVA) and polymethyl methacrylate (PMMA) were fabricated as the gate insulator where a pentacene layer was deposited at 40, 55, 70, 85, 100 oC. Pentacene thin films on PMMA showed the largest grain size and least trap concentration. In addition, pentacene TFTs of top-contact geometry are compared with PMMA and $SiO_2$ as gate insulators, respectively. We also fabricated pentacene TFT with Poly (3, 4-ethylenedioxythiophene)-Polysturene Sulfonate (PEDOT:PSS) electrode by inkjet printing method. The physical and electrical characteristics of each gate insulator were tested and analyzed by AFM and I-V measurement. It was found that the performance of TFT was mainly determined by morphology of pentacene rather than the physical or chemical structure of the polymer gate insulator

• EDISON SW 활용 경진대회 논문집
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• 제2회(2013년)
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• pp.252-255
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• 2013

Nano MOS with $Er_2O_3/SiO_2$ double-layer gate dielectrics was demonstrated by EDISON Nanophysics software. Double-layer structure decreases the gate leakage current in two orders compared with $SiO_2$ single-layer gate dielectric.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.917-919
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• 2009

Effects of nano-silver contents(15~50wt%) on screen printed-etched gate electrodes and electrical characteristics of OTFTs were investigated. As Ag contents increased, the screen-printed film was transferred exactly without spreading and obtained the densely-packed layer with a stable and excellent conductivity but, its thickness was increased and surface became rougher. It was found that the leakage current of MIM devices and off-state currents of OTFTs became larger due to poor step coverage of PVP dielectric layer on the thick and rough gate electrodes for nano-Ag inks with Ag contents more than 30wt%.

• 한국전기전자재료학회논문지
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• 제21권4호
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• pp.296-299
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• 2008

The effects of radio frequency (RF) source power for decoupled plasma nitridation (DPN) process on the electrical properties and Fowler-Nordheim (FN) stress immunity of the oxynitride gate dielectrics for deep nano-technology devices has been investigated. With increase of RF source power, the threshold voltage (Vth) of a NMOS transistor(TR) decreased and that of a PMOS transistor increased, indicating that the increase of nitrogen incorporation in the oxynitride layer due to higher RF source power induced more positive fixed charges. The improved off-current characteristics and wafer uniformity of PMOS Vth were observed with higher RF source power. FN stress immunity, however, has been degenerated with increasing RF source power, which was attributed to the increased trap sites in the oxynitride layer. With the experimental results, we could optimize the DPN process minimizing the power consumption of a device and satisfying the gate oxide reliability.

• 대한전자공학회논문지SD
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• 제46권12호
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• pp.10-17
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• 2009

Double-Gate MOSFET 구조를 사용한 Nano-Electro-Mechanical MOSFET (NEMFET)는 게이트 길이가 짧아지면서 나타나는 단채널 현상을 효과적으로 제어하는 새로운 구조의 차세대 소자이다. 특히 공핍형 Double-gate NEMFET (Dep-DGNEMFET)은 차단 상태에서 얇은 산화막을 가지므로 subthreshold 전류가 효과적으로 제어된다. 이러한 Dep-DGNEMFET 특성에 대한 해석적 수식을 유도하고 소자 구조가 변화하는 경우의 특성 변화를 분석하였다. 또한 ITRS (International Technology Roadmap for Semiconductors) 전류 기준값을 만족시키기 위하여 Dep-DGNEMFET 소자 구조를 최적화 하였다.