• Journal of Powder Materials
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• v.5 no.2
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• pp.111-121
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• 1998

Thick and dense deposit of higher than 97% of theoretical density was formed by induction plasma spraying. To investigate the effects of powder morphology on the density of deposit, two different kinds of Yttria-Stabilized-Zirconia powder, METCO202NS (atomized & agglomerated) and AMDRY146 (fused & crushed), were used and compared. After plasma treatment, porous METCO202NS powder was all the more densely deposited and its density was increased. In addition to the effect of powder morphology, the process parameters such as, sheath gas composition, probe position, particle size and spraying distance, and so on, were evaluated. The result of experiment with AMDRY146 powder, particle size and spraying distance affected highly on the density of the deposit. The optimum process condition for the deposition of -75 ${\mu}m$ of 20%-Yttria-Stabilized-Zirconia powder was 120/201/min of Ar/$H_2$ gas rate, 80 kW of plasma plate power, 8 cm of probe position and 150 Torr of spraying chamber pressure, at which its density showed 97.91% of theoretical density and its deposition rate was 20 mm/min. All the results were assessed by statistical approach what is called ANOVA.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10d
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• pp.261-266
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• 2007

UMTS release 5 에서 소개된 HSDPA 를 위해 도입된 새로운 기술 Adaptive Modulation and Coding, Hybrid Automatic Repeal reQuest, Fast Packet Scheduling 에 대해 알아보고 여기서 key role 이 되는 Fast Packet Scheduling 알고리즘 가운데 대표적인 세 가지 Round Robin(RR), Promotional Fairness(PF), Maximum Channel Quality Index(Max CQI) 알고리즘의 성능을 시스템 수율과 공평성의 관점에서 분석해보았다. 시스템 수율에서는 Max CQI, PF. RR 알고리즘 순이었으며 공평성 측면에서는 RR, PF Max CQI 알고리즘 순으로 나타났다. 같은 시스템, 같은 망 구조 내에서라면 알고리즘을 최적화하여 QoS와 성능을 극대화할 수 있도록 지속적인 연구가 필요하다.

• 전기의세계
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• v.29 no.5
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• pp.321-328
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• 1980

The Q-switching oscillator of TE $M_{00}$ mode was constructed in order to improve the properties of energy focusing and amplification, and prevent laser materials from breakdown. The Q-switching was done by means of electro-optical effect using Glan prism and KDP Pockels cell. Sharp laser pulse of risetime-1 ns and variable pulse width 2-10 ns was obtained from Q-switching laser pulse by PTM method using a laser triggered spark gap (LTSG), Glan prism and Pockels cell. A single ultra-short pulse (picosec order in pulse width) was obtained from mode-locked pulse train in combination of a mode-locked oscillator using saturable dye cell with pulse shaping system using PTM method.d.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.37-45
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• 1998

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.

• Journal of Information Processing Systems
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• v.14 no.5
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• pp.1215-1224
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• 2018

Interval-valued neutrosophic hesitant fuzzy set (IVNHFS) is an extension of neutrosophic set (NS) and hesitant fuzzy set (HFS), each element of which has truth membership hesitant function, indeterminacy membership hesitant function and falsity membership hesitant function and the values of these functions lie in several possible closed intervals in the real unit interval [0,1]. In contrast with NS and HFS, IVNHFS can be more flexibly used to deal with uncertain, incomplete, indeterminate, inconsistent and hesitant information. In this study, I propose the novel correlation coefficient of IVNHFSs and my paper discusses its properties. Then, based on the novel correlation coefficient, I develop an approach to deal with multi-attribute decision-making problems within the framework of IVNHFS. In the end, a practical example is used to show that the approach is reasonable and effective in dealing with decision-making problems.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.1892-1896
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• 2008

Inverter-fed induction motors (IFM) are prevalent in traction vehicles. However, the winding insulation of IFM is substantially more stressed than of line-powered motors by surge voltages. Consequently, the winding insulation of IFM should be estimated by surge voltages. Also, the weakness of coil insulation can be detected by the surge voltage test. This paper described the insulation evaluation of induction motors by application of surge voltages. A surge voltage generator with the maximum voltage of 5 kV and the selectable rise-time in ranges of $50\;ns\;{\sim}\;500\;ns$ was fabricated. In the experiment, we applied surge voltages into induction motors with the magnitude and the risetime according to IEEE 522. By the analysis of applied surge voltage and current waveforms, we could find difference between normal and defection windings.

• ETRI Journal
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• v.42 no.5
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• pp.790-798
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• 2020

Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.34-38
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• 1978

In this Paper, the saturation behavior in the electrical phenomena of the DH Laser diode is explained theoretically using rate equnations. The carrier density approaches to ns gradually well above the threshold and theoretically expected curve of and calculated value of $\Delta$Vj are exactly equal to the experimental results which was observed, as shown. The carrier saturation factor If is proposed and we show k$\beta$ is a measure of the ideality of the sample diode. In the light of relation, the sample diode's idoality increases as f decreases.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.188-189
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• 2017

There has been a growing demand for power semiconductor switches equipped with high-voltage blocking capability of kV range and fast-switching characteristics of ns range in various plasma application. This paper investigates the application of SiC MOSFETs in the particular plasma application which requires the blocking voltage of 4.5kV and the switching transient time of less than 100ns. In order to meet the required blocking voltage, the series connection of multiple SiC MOSFETs is adopted in this paper. Also, snubber capacitors are employed to equalize the voltage sharing among the series connected SiC MOSFETs. The simulation and experimental result successfully verifies the application of SiC MOSFETs and snubber capacitors in the plasma application requiring high-voltage and fast-switching load dynamics.

• Annual Conference of KIPS
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• 2001.04a
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• pp.363-366
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• 2001

LILI-128 스트림 암호는 IMT-2000 무선단말간 데이터 암호화를 위하여 제안된 128-비트 크기의 스트림 암호방식이며, 클럭 조절형태의 채택에 따라 속도저하라는 구조적인 문제점을 안고 있다. 본 논문에서는 귀환/이동에 있어서 랜덤한 4개의 연결 경로를 갖는 4-비트병렬 $LFSR_{d}$를 제안함으로서 속도문제를 해결하였다. 그리고 ALTERA 사의 FPGA 소자(EPF10K20RC240-3)를 선정하여 그래픽/VHDL 하드웨어 구현 및 타이밍 시뮬레이션을 실시하였으며, 50MHz 시스템 클럭에서 안정적인 50Mbps (즉, 45 Mbps 수준인 T3급 이상, 설계회로의 최대 지연 시간이 20ns 이하인 조건) 출력 수열이 발생될 수 있음을 확인하였다. 마지막으로, FPGA/VHDL 설계회로를 Lucent ASIC 소자 ($LV160C,\;0.13{\mu}m\;CMOS\;&\;1.5v\;technology$)로 설계 변환 및 타이밍 시뮬레이션한 결과 최대 지연시간이 1.8ns 이하였고, 500 Mbps 이상의 고속화가 가능함을 확인하였다.