• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1203-1210
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• 2017

Switched-inductor (SL) Z-source three-level inverter is a novel high power topology. The SL based impedance network can boost the input dc voltage to a higher value than the single LC impedance network. However, as all the neutral-point-clamped (NPC) inverters, the SL Z-source three-level inverter has to balance the neutral-point (NP) potential too. The principle of the inverter is introduced and then the effects of NP potential unbalance are analyzed. A NP balancing method is proposed. Other than the methods for conventional NPC inverter without Z-source impedance network, the upper and lower shoot-through durations are corrected by the feedforward compensation factors. With the proposed method, the NP potential is balanced and the voltage boosting ability of the Z-source network is not affected obviously. Simulations are conducted to verify the proposed method.

• Proceedings of the KIPE Conference
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• 2012.11a
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• pp.7-8
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• 2012

본 논문에서는 3레벨 NPC(Neutral Point Clamped)와 Active NPC 인버터의 스위치 손실 분배 기법에 따른 출력전력 분석을 하였다. 기존 3레벨 NPC 인버터의 경우 특정 불균형한 스위치 발열 때문에 전력밀도를 높이 설계할 수 없다. 따라서 본 논문에서는 ANPC inverter의 손실 분배기법을 적용하여 시뮬레이션으로 검증하였다.

• Journal of Power Electronics
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• v.9 no.3
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• pp.481-490
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• 2009

This paper describes a SVPWM overmodulation scheme of NPC type three-level inverter for traction drives which extends the modulation index from MI=0.907 to unity. SVPWM strategy is organized by two operation modes of under-modulation and over-modulation. The switching states under the under-modulation modes are determined by dividing them with two linear regions and one hybrid region the same as the conventional three-level inverter. On the other hand, under the over-modulation mode, they are generated by doing it with two over-modulation regions the same as the conventional over-modulation strategy of a two level inverter. Following the description of over-modulation scheme of a three-level inverter, the system description of a vector controlled induction motor for traction drives has been discussed. Finally, the validity of the proposed modulation algorithm has been verified through simulation and experimental results.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.385-387
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• 2008

Three-level Diode Clamped Multilevel Inverter, generally known as Neutral-Point-Clamped(NPC) inverter, has an inherent problem causing Neutral Point(NP) potential variation. Until now, in many literatures NP potential problem has been investigated and lots of solutions have also been proposed. However, in the case of NP potential variation was rarely published from the standpoint of reliability. In this paper, NP potential is analytically investigated both normal and fault conditions under carrier based PWM. Subsequently, relation between fault detection time and size of capacitor is analyzed. This information is explored by simulation results, which contribute to enhance the reliability of the NPC inverter system.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.487-488
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• 2016

In this paper, a new active circuit for common-mode voltage (CMV) cancellation in three-level NPC (neutral-point clamped) inverters is proposed, which can avoid the saturation of the common-mode transformer (CMT). The proposed circuit utilizes an additional three-level leg to produce the compensating CMV of the NPC inverters, which eliminates the CMV of the inverter through the CMT.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.4
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• pp.333-342
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• 2009

Three-level Diode Clamped Multilevel Inverter, generally known as Neutral-Point-Clamped (NPC) Inverter, has an inherent problem causing Neutral Point (NP) potential variation. Until now, in many literatures NP potential problem has been investigated and lots of solutions have also been proposed. However, under fault and fault tolerant control, distinctive feature for NP potential variation problem was rarely published from the standpoint of reliability. In this paper, NP potential is analytically investigated both normal and faulty conditions under carrier based PWM. Subsequently, relation between fault detection time and size of capacitor is analyzed. This information is explored by simulation and experiment results, which contribute to enhance the reliability of inverter system.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.5
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• pp.407-414
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• 2014

This study proposes a control design for the grid output current and for reducing the neutral-point voltage oscillation through the small-signal modeling of the three-phase grid connected with a three-level neutral-point-clamped (NPC) inverter with LCL filter. The three-level NPC inverter presents an inherent problem: the neutral-point voltage fluctuation caused by the neutral-point current flowing in or out from the neutral point. The small signal modeling consists of averaging, dq0 transformation, perturbing, and linearizing steps performed on a three-phase grid connected to a three-level NPC inverter with LCL filter. The proposed method controls both the grid output and neutral-point currents at every switching period and reduces the neutral-point voltage oscillation. The validity of the proposed method is verified through simulation and experiment.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.143-144
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• 2014

본 논문에서는 NPC(Neutral Point Clamped) 및 T-type IGBT 모듈을 이용하여 3상 3-레벨 인버터를 구성하고, 인버터에서 발생되어지는 도통손실과 스위칭 손실을 PSIM의 Thermal Module을 사용하여 확인한다. 또한 토폴로지 상의 차이에 의해 발생되어지는 스위치 손실을 비교 하며, 시뮬레이션에 적용한 파라미터 값들을 수식에 직접 적용하여 손실에 영향을 미치는 파라미터를 확인하고, 각 파라미터의 값의 변화가 주어진 조건에서 전체 손실에 미치는 영향을 확인한다.

• Proceedings of the KIEE Conference
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• 2007.04c
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• pp.194-197
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• 2007

This paper proposes a linearization technique for the 3 level NPC type inverter, which increases the linear control range of inverter up to the 6-step inverter. The overmodulation range is divided into two modes depending on the modulation index(MI), In mode I, the reference angles are derived from the Fourier series expansion of the reference voltage corresponds to the MI. In mode II, the holding angles are also derived in the same way. Therefore, it is possible to obtain the linear control and the maximized utilization of PWM inverter output voltage.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2085-2098
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• 2016

Laminated busbars with a low stray inductance are widely used in NPC three-level inverters, even though some of them have poor performances in heat equilibrium and overvoltage suppression. Therefore, a theoretical method is in need to establish an accurate mathematical model of laminated busbars and to calculate the impedance and stray inductance of each commutation loop to improve the heat equilibrium and overvoltage suppression performance. Firstly, an equivalent circuit of a NPC three-level inverter laminated busbar was built with an analysis of the commutation processes. Secondly, on the basis of a 3D (three dimensional) cubical thermal model and mirror circulation theory, a supersymmetric mirror circulation 3D cubical thermal model was built. Based on this, the laminated busbar was decomposed in 3D space to calculate the equivalent resistance and stray inductance in each commutation loop. Finally, the model and analysis results were put into a busbar design, simulation and experiments, whose results demonstrate the accuracy and feasibility of the proposed method.