• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1550-1552
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• 2003

고밀도의 트렌치 전력 MOSFET를 제작하는 데 있어서 새로운 소자의 구조와 공정을 제시하고 이차원 소자 및 공정 시뮬레이터를 이용하여 검증했다. 트렌치 게이트 MOSFET의 온-저항을 낮추기 위해 셀 피치가 서브-마이크론으로 발전할 경우 문제가 되는 소오스 영역을 확보하고자 p-base의 음 접촉을 위한 P+ 영역과 N+ 소오스 등이 트렌치의 측벽에 형성되고, 트렌치 게이트는 그 아래에 매몰된 구조를 제안했다. 시뮬레이션 결과는 항복전압이 45 V이고, 온-저항이 12.9m${\Omega}{\cdot}mm^2$로 향상된 trade-off 특성을 보였다.

• Journal of Sensor Science and Technology
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• v.20 no.3
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• pp.156-161
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• 2011

We fabricated a schottky barrier metal oxide semiconductor field effect transistor(SB-MOSFET) by applying indium-tin-oxide(ITO) to the source/drain on a highly resistive GaN layer grown on a silicon substrate. The MOSFET, with 10 ${\mu}M$ gate length and 100 ${\mu}M$ gate width, exhibits a threshold gate voltage of 2.7 V, and has a sub-threshold slope of 240 mV/dec taken from the $I_{DS}-V_{GS}$ characteristics at a low drain voltage of 0.05 V. The maximum drain current is 18 mA/mm and the maximum transconductance is 6 mS/mm at $V_{DS}$=3 V. We observed that the spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejection ratio was about 130 at $V_{DS}$ = 5 V. The MOSFET-type UV detector using ITO, has a high UV photo-responsivity and so is highly applicable to the UV image sensors.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.355-358
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• 1998

소신호 해석을 위해 사용되는 여러가지 방법을 비교하고 sinusoidal steady state analysis (S/sup 3/A) 방법을 이용해 반도체 소자를 소신호 해석한다. 소신호 행렬의 풀이방법으로 메모리 소비량이 적고 고주파수에서 행렬 연산으로 인한 잡음성분이 저은 전진해법을 사용한다. MEDICI에 의한 모의실험 결과와 비교하여 10GHz 이하의 주파수 영역에서는 비슷하였으나 10GHz~100GHz의 주파수영역에서 MEDICI에 비하여 정확한 결과를 보였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.36-45
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• 1993

The n-channel MOSFETs with gate-$n^{-}$S/D overlapped structure have been fabricated by ITLDD(inverse-T gate lightly doped drain) technology. The gate length(L$_{mask}$) was 0.8$\mu$m. The degradation effects of hot carriers injected into the gate oxide were analyzed in terms of threshold voltage, transconductance and drain current variations. The degradation dependences on the gate voltage and drain voltage were characterized. The devices with higher n-concentration showed higher resistivity against the hot carrier injection. As the results of investigating the lifetime of the device, the lifetime showed longer than 10 years at V$_{d}$ = 5V for the overlapped devices with the implantation of an phosphorus dose of 5$\times$10$^{13}$ cm$^{-2}$ and an energy of 80 keV in the n$^{-}$resion.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.564-576
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• 2017

${\cdot}$ GaN E-HEMT provides superior performance vs. Si MOSFET or IGBT, and also superior performance vs. SiC, below ~1200V ${\cdot}$ GaN E-HEMT is replacing Si MOSFET and IGBT in major application segments, and Industry Adoption will accelerate ${\cdot}$ Technology advances in GaN E-HEMT have made high-current true Normally-Off devices available in current ranges from 7A to 250A ${\cdot}$ While GaN has improved Properties vs. SiC or Si, different types of GaN devices offer different levels of performance or robustness ${\cdot}$ JEDEC Industrial-Grade Qualification of GaN E-HEMTs has been achieved, and Automotive Qualification is in progress.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.581-582
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• 2006

In this paper, we investigate three different types of multi-fingered layout nMOSFET devices with varying $W_f$(unit finger width) and $N_f$(number of finger). Using layout modification, we improve $f_T$(current gain cutoff frequency) value of 15GHz without scaling down, and moreover, we decrease $NF_{min}$(minimum noise figure) by 0.23dB at 5GHz. The RF noise can be reduced by increasing $f_T$, choosing proper finger width, and reducing the gate resistance. For the same total gate width using multi-fingered layout, the increase of finger width shows high $f_T$ due to the reduced parasitic capacitance. However, this does not result in low $NF_{min}$ since the gate resistance generating high thermal noise becomes larger under wider finger width. We can obtain good RF characteristics for MOSFETs by using a layout optimization technique.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.150-151
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• 2006

$Si_{0.88}Ge_{0.12}$/Si heterostructure channels grown by RPCVD were employed to n-type metal oxide semiconductor field effect transistors(MOSFETs), and their electrical properties were investigated. SiGe nMOSFETs presented very high transconductance compared to conventional Si-bulk MOSFETs, regardless substantial drawbacks remaining in subthreshold-slope, $I_{off}$, and leakage current level. It looks worthwhile to utilize excellent transconductance properties into rf applications requesting high speed and amplification capability, although optimization works on both device structure and unit processes are necessary for enhanced isolation and reduced power dissipation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.89-95
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• 1996

In this ppaer, temeprature dependent transport and heat transport models have been incorperated to the two dimensional device simulator SNU-2D provides a solid bse for nonisothermal device simulation. As an example to study the nonisothermal problem. we consider SOI MOSFET's I-V characteristics have been simulated and compared with the measurements. It is shown that negative slopes in the Ids-Vds characteristics are casused by the temperature dependence of the saturation velocity and the degradation of the temperature dependence mobility. Also it is shown that the kink effect occurs when impact ionization near the drain produces a buildup of holes in this isolated device island, and the hysteresis is caused by the creation of holes in the channel and their flow to the source.

• KIPE Magazine
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• v.23 no.3
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• pp.66-71
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• 2018

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.55-59
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• 2013

A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.