• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.2
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• pp.135-143
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.57-66
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast Fourier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi-valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like ［0,1,2,3］. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used as LUT(Look Up Table) Finally, for the compatibility with the binary system, multiple-valued hybrid-type FFT processor was proposed and designed using binary-four valued encoder, four-binary valued decoder, and the electric current mode CMOS circuit.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.1
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• pp.32-40
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• 1999

The analysis of logic function is performed by the spectral coefficients which transform the function domain data into the spectral domain data. By using the spectral techniques, analysis of MVL circuits is performaed, and the fault analysis and detecting methods of multiple-valued logic circuits are proposed in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.141-145
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• 1998

This paper CMOS full adder design method based on carry-propagation-free addition trees and a circuit technique, so called multiple-valued current-mode (MVCM) circuits. The carry-paopagation-free addition method uses a redundant digit sets called redundant positive-digit number representations. The carry-propagation-free addition is by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuit. We demonstrate the effectiveness of the proposed method through simulation(SPICE).

• Journal of the Chungcheong Mathematical Society
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• v.32 no.1
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• pp.69-86
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• 2019

In this paper, we introduce a concept of the ${\epsilon}_0$-limits of vector and multiple valued sequences in $R^m$. Using this concept, we study about the concept of the ${\epsilon}_0$-dense subset and of the points of ${\epsilon}_0$-dense ace in the open subset of $R^m$. We also investigate the properties and the characteristics of the ${\epsilon}_0$-dense subsets and of the points of ${\epsilon}_0$-dense ace.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1292-1295
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• 2002

The performance of the LSI improved drastically due to the progress of the semiconductor manufacturing technology in recent years. However, a new problem such as wiring delay and complication inside the LSI occurs. The study to solve these problems with much research organization is been doing. We tried to solve of these problems by using the neuron MOS transistor with 4-valued signal in addition to the binary signal. In this paper, We present, method which realizes 4-valued logic function. And, a designed circuit, is verified by using HSPICE.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.11
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• pp.56-64
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• 1992

The sum-of-product type MVL (Multiple-valued logic) functions can be directly transformed into the exclusive-sum-of-literal-product(ESOLP) type MVL functions with a substitution of the OR operator with the exclusive-OR(XOR) operator. This paper presents an algorithm that can reduce the number of minterms for the purpose of minimizing the hardware size and the complexity of the circuit in the realization of ESOLP-type MVL functions. In Boolean algebra, the joinable true minterms can form the cube, and if some cubes form a cube-chain with adjacent cubes by the insertion of false cubes(or, false minterms), then the created cube-chain can become a large cube which includes previous cubes. As a result of the cube grouping, the number of minterms can be reduced artificially. Since ESOLP-type MVL functions take the MIN/XOR structure, a XOR circuit and a four-valued MIN/XOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions, and PSPICE simulation results have been also presented for the validation of the proposed algorithm.

• Journal of the Korean Mathematical Society
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• v.55 no.3
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• pp.671-694
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• 2018

In this paper, we investigate the weighted vector-valued bounds for a class of multilinear singular integral operators, and its commutators, from $L^{p_1}(l^{q_1};\;{\mathbb{R}}^n,\;w_1){\times}{\cdots}{\times}L^{p_m}(l^{q_m};\;{\mathbb{R}}^n,\;w_m)$ to $L^p(l^q;\;{\mathbb{R}}^n,\;{\nu}_{\vec{w}})$, with $p_1,{\cdots},p_m$, $q_1,{\cdots},q_m{\in}(1,\;{\infty})$, $1/p=1/p_1+{\cdots}+1/p_m$, $1/q=1/q_1+{\cdots}+1/q_m$ and ${\vec{w}}=(w_1,{\cdots},w_m)$ a multiple $A_{\vec{P}}$ weights. Our argument also leads to the weighted weak type endpoint estimates for the commutators. As applications, we obtain some new weighted estimates for the $Calder{\acute{o}}n$ commutator.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.191-194
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• 2000

A level of integration will increase, if the number of elements of the circuit can be reduced. We aim to design the circuit of the new system for any further integration by using Neuron MOS Transistor. In this paper, we consider to introduce Soft-Hardware Logic and multiple-valued logic to the design methods for reducing the number of elements and inner wiring. We have designed 4-valued add-subtracter circuit using above logic. We discuss the design methods, features, and characteristics of this circuit by SPICE simulation.

• Journal of Korean Institute of Industrial Engineers
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• v.27 no.4
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• pp.394-405
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• 2001

Since most real-world application data involve continuous-valued attributes, properly addressing the discretization process for constructing a decision tree is an important problem. A continuous-valued attribute is typically discretized during decision tree generation by partitioning its range into two intervals recursively. In this paper, by removing the restriction to the binary discretization, we present a hybrid multi-interval discretization algorithm for discretizing the range of continuous-valued attribute into multiple intervals. On the basis of experiment using semiconductor etching machine, it has been verified that our discretization algorithm constructs a more efficient incremental decision tree compared to previously proposed discretization algorithms.