• 한국재료학회지
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• 제23권10호
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• pp.550-554
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• 2013

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.793-796
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• 2005

In this paper, we propose a method which can improve uniformity of a miniaturized electron beam array for inspection of very small pattern with high speed using vertical interconnection. This method enables the individual control of columns so that it can reduce the deviation of beam current, beam size, scan range and so on. The test device that used vertical interconnection method was fabricated by multiple wafer bonding and metal reflow. Two silicon and one glass wafers were bonded and metal interconnection by melting of electroplated AuSn was performed. The contact resistance was under $10{\Omega}$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.86-93
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• 2017

In this paper, we propose a novel defect detection method using component tree representations of scanning electron microscopy (SEM) images. The component tree contains rich information about the topological structure of images such as the stiffness of intensity changes, area, and volume of the lobes. This information can be used effectively in detecting suspicious defect areas. A quasi-linear algorithm is available for constructing the component tree and computing these attributes. In this paper, we modify the original component tree algorithm to be suitable for our defect detection application. First, we exclude pixels that are near the ground level during the initial stage of component tree construction. Next, we detect significant lobes based on multiple attributes and edge information. Our experiments performed with actual SEM wafer images show promising results. For a $1000{\times}1000$ image, the proposed algorithm performed the whole process in 1.36 seconds.

• 통합자연과학논문집
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• 제2권3호
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• pp.207-210
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• 2009

Multiple rugate structures can be etched on a silicon wafer and placed in the same physical location, showing that many sharp spectral lines can be obtained in the optical reflectivity spectrum. Porous silicon samples were prepared by electrochemical etch of heavily doped p-type silicon wafers. The etching solution consisted of a 3:1 volume mixture of aqueous 48% hydrofluoric acid and absolute ethanol. Galvanostatic etch was carried out in a Teflon cell by using a two-electrode configuration with a Pt mesh counterelectrode. A sinusoidal current density waveform varying between 51.5 and $74.6mA/cm^2$ is applied. The anodization current was supplied by a Keithley 2420 high-precision constant current source which is controlled by a computer to allow the formation of PSi multilayer.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.93-100
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• 2003

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

• 반도체디스플레이기술학회지
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• 제15권1호
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• pp.41-46
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• 2016

In this study, gas flow and temperature distribution in the multi-wafer planetary CVD reactor for the Si epitaxial growth were analyzed. Although the structure of the reactor was simplified as the first step of the study, the three-dimensional analysis was performed taking all these considerations of the revolution of the susceptor and the rotation of satellites into account. From the analyses, a reasonable velocity field and temperature field were obtained. However, it was found that analyses including the upper structure of the reactor were required in order to obtain more realistic temperature results. DCS mole fraction above the satellite surface and the susceptor surface without satellite was compared in order to check the gas species mixing. We found that satellite rotation helped gases to mix in the reactor.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2005년도 금형가공,미세가공,플라스틱가공 공동 심포지엄
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• pp.193-197
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• 2005

This paper presents a method by which multiple holes of ultra small size can be punched simultaneously. Silicon wafers were used to fabricate punching die. Workpiece used in the present investigation were the rolled pure copper of $3{\mu}m$ in thickness and CP titanium of $1.5{\mu}m$ in thickness. The metal foils were punched with the dies and arrays of circular and rectangular holes were made. The diameter of holes ranges from $2-10{\mu}m$. The process set-up is similar to that of the flexible rubber pad forming or Guerin process. Arrays of holes were punched successfully in one step forming. The punched holes were examined in terms of their dimensions, surface qualities, and potential defect. The effects of the die hole dimension on ultra small size hole formation of the thin foil were discussed. The optimum process condition such as proper die shape and diameter-thickness ratio (d/t) were also discussed. The results in this paper show that the present method can be successfully applied to the fabrication of ultra small size hole array in a one step operation.

• Journal of Korea Trade
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• 제24권3호
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• pp.55-72
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• 2020

Purpose - In this paper, we provide recommendations for Korea's long-term direction and strategic measures to attract inward foreign direct investment (FDI) in response to Japan's export regulations. In doing so, we analyze the current situation and characteristics of trade between Korea and Japan, focusing on the parts and materials industry, which is particularly affected by Japan's trade regulations. Design/methodology - Based on the analysis of five successful inward FDI cases (e.g. Toray, IGK, Delkor, GlobalWafers, DuPont) and statistic trend review in the parts and materials industry, we consider various factors pertaining to successful inward FDI in Korea and propose valuable investment attraction strategies. Findings - For a successful investment attraction strategy, we studied some statistical trends in the internal and external environments of the parts and materials industry and successful investment attraction cases in Korea. We have found that in order to increase the probability of success in attracting investment, we need a mid-to long-term strategy considering multiple factors such as "Production-oriented, Demand-linked, Global Value Chain (VGC) linked, and Policy-linked investment attraction." Originality/value - We suggest several specific measures and important strategic implications for the Korean government and firm's managers to attract inward FDI successfully.

• 반도체디스플레이기술학회지
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• 제22권3호
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• pp.101-105
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• 2023

Organic photo Diodes (OPDi) give multiple advantages in the growing interest of the flexible optoelectronic devices. Organic semiconductors are freeform as they can deposit on any substrate, so it could be flexible. But the inorganic material photodiodes (PDs) are usually fabricated on silicon wafers which are solid. So, normally PDs are inflexible. By those reasons, we decided to make the vacuum deposited small molecule OPDi. We have investigated the OPDi's J-V characteristic by changing the thickness of p-type layer of OPDi. This device consists of indium-tin-oxide (ITO) / 2,3:6,7-dibenzanthracene (pentacene) / buckminsterfullerene (C60) / aluminum (Al). Its J-V characteristics were measured in the probe station(4156C) that can give dark condition while measuring. And for the luminance characteristics, the photocurrent was measured with the bright halogen lamp and a probe station.

• 대한산업공학회지
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• 제29권2호
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.