• Title/Summary/Keyword: Multiple Clock System

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Multilayer thin Film technology as an Enabling technology for System-in-Package (SIP) and "Above-IC" Processing

  • Beyne, Eric
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2003.09a
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    • pp.93-100
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    • 2003
  • The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

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On the user equipment (UE) side time tracker design and implementation of the WCDMA system (WCDMA 시스템의 단말기측 time tracker 설계 및 구현)

  • Yeh, Choong-Il;Chang, Kyung-Hi;Kim, Hwan-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.2A
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    • pp.96-101
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    • 2003
  • This paper is on the user equipment (UE) side time tracker design and implementation of the wideband code division multiple access (WCDMA) system. The time tracker is constructed as a second order closed loop including time error detector (TED), loop filter (LP), numerically controlled oscillator (NCO), and sample selector (SS). Through the simulation, we found the gain of the TED as a function of the CPICH power contribution to the total transmission power of the base station. Also we derived the transfer function of the loop and the BER versus DPCH power relationships where timing offsets and loop noise bandwidths are used as parameters. In the curve, we can conclude that there are appropriate loop noise bandwidths according to the given environments for the better performance.

FPGA Design of Adaptive Digital Receiver for Wireless Identification (무선인식을 위한 적응적 디지털 수신기의 FPGA 설계)

  • Seo Young-Ho;Kim Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.4
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    • pp.745-752
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    • 2005
  • In this paper we propose and implement a digital part of a receiver system for identifying a moving object and its tracking position in wireless environment. We assumed UWB(Ultra Wide Band)-based communication system for target application and used serial communication method(RS-232). The proposed digital receiver consists of RS-232-type1/RS-232-type2 for input and output of serial communication, ID Detector for detecting IDs, and PISO&Buffer circuit to buffer input signals for appropriate operation of ID Detector. We implemented the digital receiver with minimal hardware(H/W) resource according to target application of UWB-based communication system. So it correlates input patterns with pre-stored patterns though repeated detecting method for multiple IDs. Since it has reference panerns in the Ve-stored form, it can detect various IDs instantly. Also we can program content and size of reference patterns considering compatibility with other systems .The implemented H/W was mapped into XC2S100PQ208-5 FPGA of Xilinx, occupied 727($30\%$) cells, and stably operated in the clock frequency of 75MHz(13.341ns).

Design Methodologies of High-speed Communication System with Signal Integrity (고속통신시스템의 신호충실성을 고려한 신호경로 설계 방법)

  • 박종대;박영호;남상식
    • Proceedings of the IEEK Conference
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    • 2000.11a
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    • pp.279-282
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    • 2000
  • As digital systems continue to use components with faster edge rates and clock speeds, transmission of the digital information in these systems approaches the microwave realm. At these speeds digital signal fidelity becomes both a critical success factor and design challenge. The noise sources in digital systems include the noise in power supply, ground and packaging media due to simultaneous switching of drivers, signal reflections and distortions on single and multiple transmission lines. This paper presents theory, case studies and design considerations of gigabit interconnection for network and communication systems. The case studies show HSPICE and Ampredictor simulations of alternate approaches. Various subjects including skin effect and dielectric losses, interconnect simulations and crosstalks of connector, affected signal discontinuity, are addressed.

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Real-Time Performance Evaluation of Network in Ethernet based Intranet

  • Pae, Duck-Jin;Kim, Dae-Won
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.133.3-133
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    • 2001
  • This paper analyses the real-time performance of Ethernet based intranet whether it is applicable to the real-time network. Unpredictability of transmission delay by collision-delay-retransmission mechanism in CAMA/CD(Carrier Sense Multiple Access with Collision Detect) of Ethernet is the major reason making hard to apply to real-time system. Both retransmission mechanism of TCP(Transmission Control Protocol) for reliability and sliding windows algorithm for high utilization make hard to predict transmission delay. Because real-time control network require fast responsibility and bustle of short-periodic messages, global-clock for collision avoidance and UDP(User Datagram Protocol) for high utilization of network are used. The mathematical models for time-delay that can be occured between ...

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Development of the Measurement Tool and Impedance Test Method for the Signal fidelity in PCB Tracks (PCB 트랙의 신호충실성을 위한 임피던스 계산 방법 및 측정 툴 개발)

  • 라광열;유재현;김철기;이재경;남지현;윤달환
    • Proceedings of the IEEK Conference
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    • 2002.06e
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    • pp.51-54
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    • 2002
  • As digital systems continue to use components with faster edge rate and clock speeds, transmission of the digital information can take place many troubles. The increasing requirement for controlled impedance PCBs becomes both a critical success factor and a design challenge. Especially, the noise sources in digital system include the noise in power supply, ground and packaging due to simultaneous switching of signal, signal reflections and distortions on single and multiple transmission lines. This paper simulates the tracks controlled impedance with the test coupon. So, it can saves the design time and supports the economical PCB design.

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Fine-Grain Real-Time Code Scheduling for VLIW Architecture

  • Chung, Tai M.;Hwang, Dae J.
    • Journal of Electrical Engineering and information Science
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    • v.1 no.1
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    • pp.118-128
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    • 1996
  • In safety critical hard real-time systems, a timing fault may yield catastrophic results. In order to eliminate the timing faults from the fast responsive real-time control systems, it is necessary to schedule a code based on high precision timing analysis. Further, the schedulability enhancement by having multiple processors is of wide spread interest. However, although an instruction level parallel processing is quite effective to improve the schedulability of such a system, none of the real-time applications employ instruction level parallel scheduling techniques because most of the real-time scheduling models have not been designed for fine-grain execution. In this paper, we present a timing constraint model specifying high precision timing constraints, and a practical approach for constructing static schedules for a VLIW execution model. The new model and analysis can guarantee timing accuracy to within a single machine clock cycle.

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Design and Implementation of a Realtime Video Player on Tiled-Display System (타일드-디스플레이 시스템에서 실시간 동영상 상영기의 설계 및 구현)

  • Choe, Gi-Seok;Yu, Jeong-Soo;Choi, Jeong-Hooni;Nang, Jong-Ho
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.4
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    • pp.150-157
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    • 2008
  • This paper presents a design and implementation of realtime video player that operates on a tiled-display system consisting of multiple PCs to provide a very large and high resolution display. In the proposed system, the master process transmits a compressed video stream to multiple PCs using UDP multicast. All slaves(PC) receive the same video stream, decompress, clip their designated areas from the decompressed video frame, and display it to their displays while being synchronized with each other. A simple synchronization mechanism based on the H/W clock of each slave is proposed to avoid the skew between the tiles of the display, and a flow-control mechanism based on the bit-rate of the video stream and a pre-buffering scheme are proposed to prevent the jitter The proposed system is implemented with Microsoft DirectX filter technology in order to decouple the video/audio codec from the player.

FPGA Implementation of a Burst Cell Synchroniser for the ATM-PON Upstream (ATM-PON의 상향에서 버스트 셀 동기장치의 FPGA 구현)

  • Kim, Tae-Min;Chung, Hae;Shin, Gun-Soon;Kim, Jin-Hee;Sohn, Soo-Hyeon
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.12
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    • pp.1-9
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    • 2001
  • In the APON(ATM Passive Optical Network), the transmission of the upstream traffic is based on a TDMA(Time Division Multiple Access) method that an OLT(Optical Line Termination) permits ONUs(Optical Network Units) sending cells by allocating time slots. Because the upstream is not a streaming mode, the cell synchronizer has to be operated in the burst mode. Also, the cell phase monitor is required to prevent collisions between cells which are transmitted by multiple ONUs through a single optical fiber. In this paper, a TDMA burst cell synchroniser is implemented with the FPGA(Field Programmable Gate Array) being used in the APON based on G.983.1 for transmitting upstream cells. It has two main functions which are the upstream data recovery and the phase monitoring. The former is to recover the upstream data and clock in the OLT by seeking the preamble which is the overhead of the upstream time slot and by aligning the phase of the bit and cell with the system clock. The latter is to provide the information to the ONU to compensate for the equalization delay by monitoring continuously the phase difference between adjacent cells to avoid the cell collision on the upstream.

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Influences of Autonomic Function, Salivary Cortisol and Physical Activity on Cognitive Functions in Institutionalized Older Adults with Mild Cognitive Impairment: Based on Neurovisceral Integration Model (요양병원에 입원한 경도 인지장애 노인의 자율신경 기능, 타액 코티졸과 신체활동 정도가 인지기능에 미치는 영향: Neurovisceral Integration Model 기반)

  • Suh, Minhee
    • Journal of Korean Academy of Nursing
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    • v.51 no.3
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    • pp.294-304
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    • 2021
  • Purpose: This study aimed to investigate objectively measured physical activity (PA) in institutionalized older adults with mild cognitive impairment (MCI) and to elucidate the influence of autonomic nervous function, salivary cortisol, and PA on cognitive functions based on neurovisceral integration model. Methods: Overall cognitive function was evaluated using the mini-mental state examination (MMSE) and executive function was evaluated using semantic verbal fluency test and clock drawing test. Actigraph for PA, HRV and sAA for autonomous function, and the geriatric depression scale for depression were used. Saliva specimens were collected in the morning for sAA and cortisol. Results: Ninety-eight older adults from four regional geriatric hospitals participated in the study. They took 4,499 steps per day on average. They spent 753.93 minutes and 23.12 minutes on average in sedentary and moderate-to-vigorous activity, respectively. In the multiple regression analysis, lower salivary cortisol level (β = - .33, p = .041) and greater step counts (β = .37, p = .029) significantly improved MMSE score. Greater step count (β = .27, p = .016) also exerted a significant influence on verbal fluency, and greater sAA (β= .35, p = .026) was significantly associated with a better clock drawing test result. Conclusion: Salivary cortisol, sAA and physical activity were significantly associated with cognitive functions. To prevent older adults from developing dementia, strategies are needed to increase their overall PA amount by decreasing sedentary time and to decrease salivary cortisol for cognitive function, and to maintain their sympathetic nervous activity for executive function.