• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.141-145
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• 1998

This paper CMOS full adder design method based on carry-propagation-free addition trees and a circuit technique, so called multiple-valued current-mode (MVCM) circuits. The carry-paopagation-free addition method uses a redundant digit sets called redundant positive-digit number representations. The carry-propagation-free addition is by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuit. We demonstrate the effectiveness of the proposed method through simulation(SPICE).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.338-341
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• 1998

This paper presents CMOS full adder design method based on carry-propagation-free addition trees and a circuit technique, so called multiple-valued current-nude(MVCM) circuits. The carry-propagation-free addition method uses a redundant digit sets called redundant positive-digit number representations. The carry-propagation-free addition is by three steps, and the adder can be designed directly and efficiently from the algorithm using WVCM circuit, Also Multiplier can be designed by these adder. We demonstrate the effectiveness of the proposed method through simulation(SPICE).

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.11 no.2
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• pp.108-112
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• 2011

Kaneko et a1.[4] etc many authors extended with multi-valued maps for the notion of compatible maps in complete metric space. Recently, O'Regan et a1.[5] presented fixed point and homotopy results for compatible single-valued maps on complete metric spaces. In this paper, we will establish some common fixed point theorems using compatible maps in intuitionistic fuzzy metric space.

• The KIPS Transactions:PartA
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• v.14A no.4
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• pp.203-208
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• 2007

This paper proposes a $64{\times}64$ Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung $0.35{\mu}m$ standard CMOS process at a 3.3V supply voltage and unit current $5{\mu}m$. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of $7.5{\times}9.4mm^2$, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.03a
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• pp.103-106
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• 1998

본 논문은 다치논리와 신경망을 융합한 다치 뉴로 모델을 제안한다. 다치논리를 이용하여 다치 연산을 위한 알고리즘을 제안하고, 다치-OR, 다치-AND, 다치-NOT 회로를 이용한 다치 뉴로 시스템을 구성하고, 모의 실험을 통하여 확인하였다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1851-1864
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• 1997

This paper presents an algorithm simplifying the ESOP function by several rules. The algorithm is repeatedly performing operations based on the state of each terms by the product transformation operation of two functions and thus it is simplifying the ESOP function through the reduction of the product terms. Through the minimization of the product terms of the multi-valued input binary multi-output function, an optimization of the input has been done using EXOR PLA with input decoder. The algorithm when applied to four valued arithmetic circuit has been used for a EXOR logic circuit design and the two bits input decoder has been used for a EXOR-PLA design. It has been found from a computer simulation(IBM PC486) that the suggested algorithm can reduce the product terms of the output function remarkably regardless of the number of input variables when the variable AND-EXOR PLA is applied to the poperation circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1288-1293
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• 2005

This paper presents a design method for multiple-output combinational digital logic systems using time domain based on multiplexing(TDBM) and common multi-terminal extension decision diagrams(CMTEDD). The CMIEDDs represents extension valued multiple-output functions, while TDBM systems transmit several signals on a single lines. The proposed method can reduce the 1)hardware, 2)logic levels and 3)pins. In the logic system design, we use two types of decision diagrams(DDs), that is the common binary decision diagrams(CBDDs) and CMTEDDs. Also, we propose an algorithms to derive common multiple-terminal binary decision diagrams(CMTBDD) from CBDDs, and CMTEDDs from CMTBDDs. The CMTEDDs over CBDDs is more compactness in terms of number of non-terminal nodes, where the nodes for output selection variables are not included in the non-terminal nodes. In the logic design, each non-terminal nodes of an CBDDs and an CMTEDDs is realized by a multiplexer(MUX). In addition, we compare the proposed TDBM realization with the conventional one.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.135-143
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• 2003

This paper describes the design techniques of the data converters for Multiple-Valued Logic(MVL). A 3.3V low power 4 digit CMOS analog to quaternary converter (AQC) and quaternary to analog converter (QAC) mainly designed with the neuron MOS down literal circuit block has been introduced. The neuron MOS down literal architecture allows the designed AQC and QAC to accept analog and 4 level voltage inputs, and enables the proposed circuits to have the multi-threshold properity. Low power consumption of the AQC and QAC are achieved by utilizing the proposed architecture.

• Proceedings of the KAIS Fall Conference
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• 2002.05a
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• pp.215-217
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• 2002

본 논문에서는 CM-MVL(Current Mode Multi-Valued Logic)을 이용한 Host와 LCD Controller 간에 인터페이스 회로를 제안한다. 제안한 회로는 기존의 LVDS(Low Voltage Differential Signaling)과 TMDS(Transition Minimized Differential Signaling)와 같은 전류 특성을 가지며, 3비트 동시 전송이 가능하여 동일한 전송 속도 하에서 보다 많은 데이터를 전송할 수 있다. 그리고 전류에 의한 데이터 전송을 통하여 노이즈에 강한 특성을 나타낸다. 제안한 회로는 HSPICE 시뮬레이션을 통해서 회로의 동작을 확인하였다.