• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• 전력전자학회논문지
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• 제7권1호
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• pp.65-73
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• 2002

본 논문에서는 플라잉 커패시터 멀티-레벨 인버터의 가장 큰 문제점인 커패시터 전압 불균형을 캐리어 비교방식을 토대로 한 펄스 폭 변조 방식(PWM)을 이용하여 제어하는 새로운 PWM방법을 제안한다. 제안된 방법은 멜티-레벨 인버터로 확장이 용이한 캐리어 비교 방식의 PWM방법으로서 플라잉 커패시터 인버터에서 소자의 스위칭시각 커패시터의 충·방전으로 인해 발생되는 전압불균형에 대해 상전압 리던던시와 선간전압 리던던시를 이용하여 커패시터 전압의 변화량을 일정주기에 대해 평균적으로 영으로 제어하게 된다. 또한 이 방법은 상전압 리던던시를 고르게 이용하여 소자의 스위치 손실과 도통 손실을 같게 하는 장점을 지닌다. 본문에서 플라잉 커패시터 인버터에 서 발생하는 커패시터 전압 불균형에 대해 분석하고 이 인버터에 적합한 캐리어 비교방식의 PWM방법을 설명한다.

• Journal of Electrical Engineering and Technology
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• 제3권3호
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• pp.391-400
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• 2008

Multi-pulse topology of converters using elementary six-pulse GTO - VSC (gate turn off based voltage source converter) operated under fundamental frequency switching (FFS) control is widely adopted in high power rating static synchronous compensators (STATCOM). Practically, a 48-pulse ($6{\times}8$ pulse) configuration is used with the phase angle control algorithm employing proportional and integral (PI) control methodology. These kinds of controllers, for example the ${\pm}80MVAR$ compensator at Inuyama switching station, KEPCO, Japan, employs two stages of magnetics viz. intermediate transformers (as many as VSCs) and a main coupling transformer to minimize harmonics distortion in the line and to achieve a desired operational efficiency. The magnetic circuit needs altogether nine transformers of which eight are phase shifting transformers (PST) used in the intermediate stage, each rating equal to or more than one eighth of the compensator rating, and the other one is the main coupling transformer having a power rating equal to that of the compensator. In this paper, a two-level 48-pulse ${\pm}100MVAR$ STATCOM is proposed where eight, six-pulse GTO-VSC are employed and magnetics is simplified to single-stage using four transformers of which three are PSTs and the other is a normal transformer. Thus, it reduces the magnetics to half of the value needed in the commercially available compensator. By adopting the simple PI-controllers, the model is simulated in a MATLAB environment by SimPowerSystems toolbox for voltage regulation in the transmission system. The simulation results show that the THD levels in line voltage and current are well below the limiting values specified in the IEEE Std 519-1992 for harmonic control in electrical power systems. The controller performance is observed reasonably well during capacitive and inductive modes of operation.

• 한국철도학회논문집
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• 제9권6호
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• pp.761-765
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• 2006

At present, harmonic currents cause serious problems in power conversion system using the semiconductor switching device. Also some of the conversion system provokes harmonic currents against to the main power supply system and causes hindrances for the system. Main power impedance of the traditional LC passive filter method, influences on the filter characteristics and amplifies the harmonics when resonance phenomenon is occurred. And the traditional existing 2 level inverter systems show the limit in capacity of voltage and current in case of occurring sudden load change. So, to solve this problem active filter which uses cascaded H-bridge multi level inverter has been designed and ex-filter system circuits were totally investigated. With multi level active filtering system not only the size of filter but also the size of filter for transformer can be reduced by half and so as to the weight, while the capacity of inverter can be double sized and wave forms can be compensated exactly and precisely. Also by the benefit of the increase in rating capacity, the various currents owing to the load fluctuation can be dealt more steadily. In order to simulate the wave form of harmonics based on the measured data on the AC 25kV high speed Domestic Commercial railway, it was simulated with PSCAD/EMTDC and PSIM. Based on the results of this demonstration, the power supply system and inverter system would be more stable and also promoting its efficiency.

• 전력전자학회논문지
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• 제9권5호
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• pp.438-447
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• 2004

본 논문에서는 하프ㆍ풀-브리지 셀을 이용하는 새로운 멀티레벨 인버터를 제안하고 독립형 태양광 인버터로서의 가능성을 평가한다. 기본 회로 구조는 기존의 11-레벨형 PWM 인버터에 기초하며 세 개의 풀-브리지 모듈 중 하나의 모듈을 하프-브리지 구조로 대체한다. 이 간단한 회로 구조의 변경으로 제안된 멀티레벨 인버터는 세 가지의 장점을 가지게 된다. 첫째, 출력 전압 레벨 수의 증가를 통해 보다 정현적인 출력 전압 파형을 형성 시킬 수 있다. 둘째, 풀-브리지 모듈 대신 하프-브리지 셀을 이용하므로 두 개의 전력 스위치를 줄일 수 있다. 셋째, 쵸핑용으로 이용되는 인버터와 결합된 변압기에 의해 부하로 전달되는 전력량을 저감 시킬 수 있어 전체 효율 개선에 유리하다. 즉, 대부분의 전력은 저주파 스위칭 동작으로 기본 출력전압을 형성하는 인버터와 이와 결합된 변압기에 의해 부하단으로 전달되고, 고주파 스위칭을 하는 쵸핑용 인버터와 이와 결합된 변압기를 통한 출력은 최종 출력전압을 보다 정현화 하기 위한 목적으로 사용되도록 한다. 기존의 11-레벨형 PWM 인버터와 비교를 통해 제안하는 인버터를 평가하고, 컴퓨터 시뮬레이션 및 실험 결과를 통해 독립형 태양광 인버터로서의 가능성을 입증한다.

• 한국정보전자통신기술학회논문지
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• 제6권3호
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• pp.135-140
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• 2013

본 논문은 스마트 그리드의 핵심 설비중 하나인 반도체 지능형 변압기의 시스템 구성과 이에 필요한 PWM 컨버터의 PWM 생성 방식에 관한 논문으로, 반도체 지능형 변압기의 경우 입력단이 수전계통에 직접 접속되기 때문에 고전압을 견딜 수 있는 방식으로 구성되어야 하고 이를 위해서는 다단 연결방식의 PWM 컨버터의 구성이 필수적이다. 종래의 PWM 생성 방식의 경우 지령전압의 크기에 따라서 각 단별 스위칭 부하가 균등하게 분포되지 않기 때문에 이를 해결하기 위한 복잡한 리던던시를 스위칭 패턴에 추가해야 했으나, 본 논문에서 제안하는 방식의 경우 부하의 분담이 자동적으로 이루어지기 때문에 그러한 부담없이 시스템을 구성하는 것이 가능하다.

• Journal of Power Electronics
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• 제18권4호
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• pp.1037-1050
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• 2018

This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1552-1557
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• 2015

The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.57-57
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• 2010

In this study, nano-sized phase change materials were evaluated using nanoimprint lithography and c-AFM technique. The 200nm in diameter phase change nano-pillar device of GeSbTe, AgInSbTe, InSe, GeTe, GeSb were successfully fabricated using nanoimprint lithography. And the electrical properties of the phase change nano-pillar device were evaluated using c-AFM with pulse generator and voltage source.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1153-1156
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• 2003

In this paper, we present a reducing power consumption of a scheduling for module selection under the time constraint. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed scheduling of reducing power consumption is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our approach various HLS benchmark environment using chaining and multi-cycling in the scheduling techniques..