• 한국멀티미디어학회논문지
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• 제19권7호
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• pp.1154-1158
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• 2016

This paper presents a System-On-a-chip for embedded image processing applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• 지구물리와물리탐사
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• 제21권4호
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• pp.213-219
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• 2018

본 연구에서는 제온 파이 x200 프로세서를 이용하여 3차원 파동 전파 모델링을 수행하고 기존의 제온 CPU를 사용한 경우와 병렬 연산 성능을 비교하였다. 제온 파이 1세대 프로세서인 제온 파이 나이츠 코너 보조프로세서와 달리 제온 파이 2세대 프로세서인 x200 프로세서는 직접 운영체제 실행이 가능하므로 내장 메모리와 주메모리 사이의 추가적인 통신이 필요 없다. 또한 제온 파이 x200 프로세서는 대용량 주메모리와 고대역폭 메모리를 이용하여 대규모 컴퓨팅을 독립적으로 실행할 수 있다. 병렬 연산 성능 비교를 위해 MPI (Message Passing Interface)와 OpenMP (Open Multi-Processing)를 이용해 모델링을 수행하였다. SEG/EAGE 암염돔 모델을 이용한 수치 실험 결과 제온 파이에서 다량의 연산 코어와 고대역폭 메모리를 이용해 12 코어 CPU 대비 2.69 ~ 3.24배 우수한 모델링 성능을 얻을 수 있었다.

• 디지털산업정보학회논문지
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• 제15권4호
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• pp.85-92
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• 2019

This paper presents a SDR-based Long Term Evolution Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a multicore Digital Signal Processor (DSP). For decoder implementation, multicore DSP TMS320C6670 is used, which provides various hardware accelerators such as turbo decoder, fast Fourier transformer and Bit Rate Coprocessors. The TMS320C6670 is a DSP specialized in implementing base station platforms and is not an optimized platform for implementing mobile terminal platform. Accordingly, in this paper, the hardware accelerator was changed to the terminal implementation to implement the LTE-A PDSCH decoder supporting the multi-antenna and the functions not provided by the hardware accelerator were implemented through core programming. Also pipeline using multicore was implemented to meet the transmission time interval. To confirm the feasibility of the proposed implementation, we verified the real-time decoding capability of the PDSCH decoder implemented using the LTE-A Reference Measurement Channel (RMC) waveform about transmission mode 2 and 3.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.2221-2225
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• 2005

Various types of fieldbus are used in factories in order to achieve the communication between the parts of process. But the protocol of the fieldbus doesn't have the standardized unique protocol. Thus, it is hard to exchange information each other with real time base when the different type protocols are adopted in the same network. In this paper, we implement two types of gateway for CAN and Profibus-DP: PC-based gateway and stand-alone gateway using the 80186 core based Dstni-LX network processor. The performance of proposed PC-based and stand-alone gateway is verified experimentally.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.723-724
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• 2006

Exploiting the instruction level parallelism encountered with the limit. Single chip multiprocessor was introduced to overcome the limit of traditional processor using the instruction level parallelism. Also, a branch miss prediction is one of the causes that reduce the processor performance. In order to overcome the problems, in this paper, we make single chip multiprocessor having the idle core execute the two control flow of conditional branch. This scheme is a kind of multi-path execution technique based on single chip multiprocessor architecture.

• 한국정보통신학회논문지
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• 제24권8호
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• pp.1109-1112
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• 2020

This paper presents a low cost hardware message passing engine of enhanced atomic pipelined broadcast based on processing node status. In this algorithm, the previous atomic pipelined broadcast algorithm is modified to reduce the waiting time until next broadcast communication. For this, the processor change the transmission order of processing nodes based on the nodes' communication channel. Also, the hardware message passing engine architecture of the proposed algorithm is modified to be adopted to multi-core processor. The synthesized logic area of the proposed hardware message passing engine was reduced by about 16%, compared by the pre-existing hardware message passing engine.

• 한국인터넷방송통신학회논문지
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• 제14권6호
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• pp.259-265
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• 2014

현재 널리 이용되는 멀티코어 프로세서 구조의 설계 초기에 그 성능을 분석하기 위하여 명령어 트레이스 모의실험을 이용하는 경우, 시간과 공간을 많이 차지하기 때문에 비실용적이다. 본 논문에서는 프로화일링 기법에 기반하는 통계적 모의실험에 의하여 다양한 하드웨어 사양을 갖는 멀티코어 프로세서의 성능을 측정하는 기법에 대하여 연구하였다. 이것을 위하여 SPEC 2000 벤치마크 프로그램의 특성을 통계적 프로화일링 기법으로 모델링하고 여기서 얻은 통계적 프로화일을 바탕으로 벤치마크 트레이스를 합성하여 멀티코어 프로세서에 대한 모의실험을 수행하였다. 그 결과, 통계적 모의실험에 의하여 측정한 성능이 명령어 트레이스 모의실험에 의하여 측정한 성능에 근접한 결과를 가져왔으며 모의실험 시간을 크게 단축시켰다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• 한국항행학회논문지
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• 제14권1호
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• pp.57-65
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• 2010

본 연구에서는 새로운 형태의 로봇 제어기의 구조인 이기종 멀티프로세서 제어기의 개념적인 구조를 제시하며, 제어기 내에 분산된 멀티프로세서들을 sRIO 통신을 이용하여 통합하는 구조적인 방법을 소개한다. 또한 sRIO 통신으로 통합된 이기종 멀티프로세서의 구현을 위한 방법으로 FPGA 내에 설계된 sRIO IP Core를 활용한 시뮬레이션을 수행하고 그 결과를 확인하였다.

• Journal of Computing Science and Engineering
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• 제6권1호
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• pp.12-25
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• 2012

For real-time systems it is important to obtain the accurate worst-case execution time (WCET). Furthermore, how to improve the WCET of applications that run on multicore processors is both significant and challenging as the WCET can be largely affected by the possible inter-core interferences in shared resources such as the shared L2 cache. In order to solve this problem, we propose an innovative approach that adopts a code positioning method to reduce the inter-core L2 cache interferences between the different real-time threads that adaptively run in a multi-core processor by using different strategies. The worst-case-oriented strategy is designed to decrease the worst-case WCET among these threads to as low as possible. The other two strategies aim at reducing the WCET of each thread to almost equal percentage or amount. Our experiments indicate that the proposed multicore-aware code positioning approaches, not only improve the worst-case performance of the real-time threads but also make good tradeoffs between efficiency and fairness for threads that run on multicore platforms.