Journal of Computing Science and Engineering

Korean Institute of Information Scientists and Engineers (한국정보과학회)
권호 표지
DOI QR코드

DOI QR Code

Multicore-Aware Code Co-Positioning to Reduce WCET on Dual-Core Processors with Shared Instruction Caches

  • Ding, Yiqiang (Department of Electrical and Computer Engineering, Virginia Commonwealth University) ;
  • Zhang, Wei (Department of Electrical and Computer Engineering, Virginia Commonwealth University)
  • Received : 2012.02.02
  • Accepted : 2012.02.17
  • Published : 2012.03.30
Download PDF
⟨ Previous Next ⟩

Abstract

For real-time systems it is important to obtain the accurate worst-case execution time (WCET). Furthermore, how to improve the WCET of applications that run on multicore processors is both significant and challenging as the WCET can be largely affected by the possible inter-core interferences in shared resources such as the shared L2 cache. In order to solve this problem, we propose an innovative approach that adopts a code positioning method to reduce the inter-core L2 cache interferences between the different real-time threads that adaptively run in a multi-core processor by using different strategies. The worst-case-oriented strategy is designed to decrease the worst-case WCET among these threads to as low as possible. The other two strategies aim at reducing the WCET of each thread to almost equal percentage or amount. Our experiments indicate that the proposed multicore-aware code positioning approaches, not only improve the worst-case performance of the real-time threads but also make good tradeoffs between efficiency and fairness for threads that run on multicore platforms.

Keywords

References

  1. J. M. Calandrino, J. H. Anderson, and D. P. Baumberger, "A hybrid real-time scheduling approach for large-scale multicore platforms," Proceedings of the 19th Euromicro Conference on Real-Time Systems, Pisa, Italy, 2007, pp. 247-258.
  2. S. Mohan, F. Mueller, W. Hawkins, M. Root, C. A. Healy, and D. Whalley, "ParaScale: exploiting parametric timing analysis for real-time schedulers and dynamic voltage scaling," Proceedings of the 26th IEEE International Real-Time Systems Symposium, Miami, FL, 2005, pp. 233-242.
  3. W. Zhao, D. Whalley, C. A. Healy, and F. Mueller, "WCET code positioning," Proceedings of the 25th IEEE International Real-Time Systems Symposium, Lisbon, Portugal, 2004, pp. 81-91.
  4. P. Lokuciejewski, H. Falk, and P. Marwedel, "WCET-driven cache-based procedure positioning optimization," Proceedings of the 2008 Euromicro Conference on Real-Time Systems, Prague, Czech Republic, 2008, pp. 321-330.
  5. Y. Ding and W. Zhang, "WCET-oriented code positioning on multicore processors with shared instruction cashes," Proceedings of the 16th IEEE Real-Time and Embedded Technology and Applications Symposium, Stockholm, Sweden, 2010, pp. 69-72.
  6. Y. Ding and W. Zhang, "Multicore-aware code positioning to improve worst-case performance," The 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, Newport Beach, CA, 2011, pp. 225-232.
  7. S. McFarling, "Program optimization for instruction caches," Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, MA, 1989, pp. 183-191.
  8. W. W. Hwu and P. P. Chang, "Achieving high instruction cache performance with an optimizing compiler," Proceedings of the 16th Annual International Symposium on Computer Architecture, Jerusalem, Israel, 1989, pp. 242-251.
  9. K. Pettis and R. C. Hansen, "Profile guided code positioning," Proceedings of the ACM SIGPLAN 1990 Conference on Programming Language Design and Implementation, White Plains, New York, 1990, pp. 16-27.
  10. B. Calder and D. Grunwald, "Reducing branch costs via branch alignment," Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, 1994, pp. 242-251.
  11. C. Young, D. S. Johnson, M. D. Smith, and D. R. Karger, "Near-optimal intraprocedural branch alignment," Proceedings of the ACM SIGPLAN 1997 Conference on Programming Languages Design and Implementation, Las Vegas, NV, 1997, pp. 183-193.
  12. D. B. Kirk, "SMART (strategic memory allocation for realtime) cache design," Proceedings of the Real-Time Systems Symposium, Santa Monica, CA, 1989, pp. 229-237.
  13. D. B. Kirk and J. K. Strosnider, "SMART (strategic memory allocation for real-time) cache design using the MIPS R3000," Proceedings of the 11th Real-Time Systems Symposium, Lake Buena Vista, FL, 1990, pp. 322-330.
  14. A. Wolfe, "Software-based cache partitioning for real-time applications," Journal of Computer and Software Engineering, vol. 2, no. 3, pp. 315-327, 1994.
  15. F. Mueller, "Compiler support for software-based cache partitioning," Proceedings of the ACM SIGPLAN 1995 worshop on Languages, Compilers, and Tools for Real-Time Systems, La Jolla, CA, 1995, pp. 125-133.
  16. T. Tian and C. Shih, "Software techniques for shared-cache multi-core systems," Intel Software Network, 2009, http:// software.intel.com/en-us/articles/software-techniques-for-sharedcache- multi-core-systems/.
  17. J. Yan and W. Zhang, " WCET analysis for multi-core processors with shared L2 instruction caches," Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium, St. Louis, MO, 2008, pp. 80-89.
  18. Y. S. Li and S. Malik, "Performance analysis of embedded software using implicit path enumeration," Proceedings of the 32nd Annual ACM/IEEE Design Automation Conference, San Francisco, CA, 1995, pp. 456-461.
  19. Y. S. Li, S. Malik, and A. Wolfe, "Cache modeling for realtime software: beyond direct mapped instruction caches," Proceedings of the 17th IEEE Real-Time Systems Symposium, Washington D.C., 1996, pp. 254-263.
  20. K. Kim, D. Kim, and C. Park, "Real-Time scheduling in heterogeneous dual-core architectures," Proceedings of the 12th International Conference on Parallel and Distributed Systems, Minneapolis, MN, 2006, pp. 91-96.
  21. V. Kathail, M. S. Schlansker, and B. R. Rau, "HPL-PD architecture specification: version 1.1," Hewlett-Packard Company, Palo Alto, CA, Technical Report HPL-93-80, 1994.
  22. L. Gwennap, "Digital 21264 set new standard," Microprocessor Report, vol. 10, no. 14, 1996.
  23. "Trimaran," http://www.trimaran.org.
  24. National University of Singapore, "Chronos," http://www. comp.nus.edu.sg/-rpembed/chronos/.
  25. "SimpleScalar," http://www.simplescalar.com/.
  26. IBM, "IBM ilog CPLEX optimizer," http://www-01.ibm.com/ software/integration/optimization/cplex-optimizer/.
  27. Malardalen Real-Time Research Centre (MRTC), "The worst-case execution time (WCET) analysis project," http:// www.mrtc.mdh.se/projects/wcet/.

Cited by

  1. Thread-level priority assignment in global multiprocessor scheduling for DAG tasks vol.113, 2016, https://doi.org/10.1016/j.jss.2015.12.004
  2. GPU-SAM: Leveraging multi-GPU split-and-merge execution for system-wide real-time support vol.117, 2016, https://doi.org/10.1016/j.jss.2016.02.009