• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2005.10a
• /
• pp.882-884
• /
• 2005

A new rectangular shape microlens array having high sag for solid-state lighting is presented. Proposed microlens, which has high sag, over $375{\mu}m$ and large diameter, over 3 mm can enormously enhance output optical extraction efficiency. Rectangular shape of microlens can maximize the fill factor of light-emitting-diode (LED) package and minimize the optical loss at the same time. This wafer level microlens array is fabricated on LED package. It has many advantages in optical properties, low cost, high aligning accuracy, and mass production.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.11 s.353
• /
• pp.8-13
• /
• 2006

Recent RF SAW filters are made using a HTCC package with a CSP(chip scale Package) technology. This paper describes a development of a new $1.4{\times}1.1\;and\;2.0{\times}1.4mm$ RF SAW liters made by PCB substrate instead of HTCC package, and this technology can reduce the cost of materials down to 40%. We have investigated the multi-layered PCB substrate structures and raw materials to find out the optimal flip-bonding condition between the $LiTaO_3$ wafer and PCB substrates. Also the optimal materials and processing conditions of epoxy laminating film were found out through the experiments which can reduce the bending moment caused by the difference of the thermal expansion between the PCB substrate and laminating film. The new PCB SAW filter shows good electrical and reliability performances with respect to the present SAW filters.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.2
• /
• pp.43-51
• /
• 2014

In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

• Journal of the Korean Society for Precision Engineering
• /
• v.26 no.12
• /
• pp.23-31
• /
• 2009

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.27 no.9
• /
• pp.1-5
• /
• 2013

We developed high-efficient 6W-LED package with simple structure by applying Heat Slug and silicone-reflector. LED package was manufactured in $8.5{\times}8.5mm$ sized multi-chip structure having thickness of $500{\mu}m$ achieved by bonding silicon-reflector with prepreg on top of the plate after implementing the reflector placed on copper substrate Half Etching by thickness of $200{\mu}m$. The luminous flux, luminous efficacy, correlated color temperature, color rendering index and thermal resistance of developed LED was evaluated, and it verified the application of products by applying it to 120W-LED road luminaires through simulation. The luminous efficacy of LED package reached over 130lm/W, and it is possible to be manufactured into 120W-LED road luminaires using 18 packages. In addition, the simulation results showed average of horizontal illuminance and overall illuminance uniformity that is suitable for three-lane road.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.28 no.7
• /
• pp.1-12
• /
• 2014

This paper is proposed to design the new heat-sink apparatus for improving the heat transfer characteristics in the power LED chip, and results of the operation characteristics were discussed. The core design is that the soldering through-hole on the FR-4 PCB board is formed to the effective heat transfer. That is directly filled with Ag-nano materials, which shows the high thermal conductivity. The heat transfer medium consisting of Ag-nano materials is classified into two structures. Mediums are called as the heat slug and the multi-pin in this work. The heat of the high temperature generated from the LED chip was directly transferred to the heat slug of the one large size. And the accumulated heat from the heat slug was quickly dissipated by the medium of the multi-pin, which is the same body with the heat slug. This multi-pin was designed for the multi-dissipation of heat by increasing the surface areas with a little pins. Subsequently, the speed of the heat transfer with this new heat-sink apparatus is three times faster than the conventional heat-sink. Therefore, the efficiency of the illuminating light will be improved by adapting this new heat-sink apparatus in the large area's LED.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.2
• /
• pp.7-15
• /
• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.431-432
• /
• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Semiconductor & Display Technology
• /
• v.17 no.4
• /
• pp.42-45
• /
• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.

• Journal of the Microelectronics and Packaging Society
• /
• v.24 no.2
• /
• pp.11-15
• /
• 2017

As the heat dissipation problem is increased in 3D multi flip chip packages, an improvement of thermal conductivity in bonding interfaces is required. In this study, the effect of alumina filler addition was investigated in non-conductive paste(NCP). The fine alumina filler having average particles size of 400 nm for the fine pitch interconnection was used. As the alumina filler content was increased from 0 to 60 wt%, the thermal conductivity of the cured product was increased up to 0.654 W/mK at 60 wt%. It was higher value than 0.501 W/mK which was reported for the same amount of silica. It was also found out that the addition of fine sized alumina filler resulted in the smaller decrease in thermal conductivity than the larger sized particles. The viscosity of NCP with alumina addition was increased sharply at the level of 40 wt%. It was due to the increase of the interaction between the filler particles according to the finer particle size. In order to achieve the appropriate viscosity and excellent thermal conductivity with fine alumina fillers, the highly efficient dispersion process was considered to be important.