• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.1
• /
• pp.107-112
• /
• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• Journal of the Semiconductor & Display Technology
• /
• v.6 no.1 s.18
• /
• pp.17-22
• /
• 2007

Recent new packages such as MCP(Multi-Chip Package), QDP(Quadratic Die Package) and DDP(Dual Die Package) have stack type configuration. This kind of multi-layer package is thicker than single layer package. So there is need for the low height looping technology in wirebonder to make these packages thinner. There is stiff zone above ball in wirebonder wire which is called HAZ(Heat Affect Zone). When making low height loop (below $80\;{\mu}m$) with traditional forward loop, stiff wire in HAZ(Heat Affected Zone) above ball is bended and weakened. So the traditional forward looping method cannot be applied to low height loop. SSB(stand-off stitch) wire bonding method was applied to many packages which require very low loops. The drawback of SSB method is making frequent errors at making ball, neck damage above ball on lead and the weakness of ball bonding on lead. The alternative looping method is BNL(ball neckless) looping technology which is already applied to some package(DDP, QDP). The advantage of this method is faster in bonding process and making little errors in wire bonding compared with SSB method. This paper presents the result of BNL looping technology applied in assembly house and several issues related to low loop height consistence and BNL zone weakness.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2013.05a
• /
• pp.837-838
• /
• 2013

• Journal of the Korean Society for Precision Engineering
• /
• v.20 no.10
• /
• pp.183-190
• /
• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.57 no.4
• /
• pp.653-659
• /
• 2008

This paper describes the design of high power transistor packages using high power chip transistor dies, chip capacitors and a new wire bonding technique. Input impedance variation and output power performances according to wire inductance and resistance for internal matching are also discussed. A multi crossing type(MCT) wire bonding technique is proposed to replace the conventional stepping stone type(SST) wire bonding technique, and eventually to improve the output power performances of high power transistor packages. Using the proposed MCT wire bonding technique, it is possible to design high power transistor packages with highly improved output power compared to SST even the package size is kept to be the same.

• Journal of the Microelectronics and Packaging Society
• /
• v.9 no.1
• /
• pp.43-48
• /
• 2002

Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.12 no.3
• /
• pp.1479-1487
• /
• 2011

In the field of the entire electronic component industry including mobile IT products, the importance of a versatile package with the multifunctional or high capacity memories is gradually increased. Multi Chip Package which has several chips in a single package is frequently used for that purpose. In MCP, epoxy adhesive films play a major role in adhesion between the chips or between chip and substrate. A series of silane coupling agents with a functional group such as epoxy, amine, mercaptan, and isocyanate were applied to the epoxy adhesives and material properties such as wettability and reliability of the adhesives were investigated. From the results, the silane coupling agent with an epoxy functional group showed highest wettability and peel strength in epoxy adhesive. For those reasons, it lead to a superior reliability in the epoxy adhesive against interfacial fracture behaviors through moisture resistance test.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2012.10a
• /
• pp.485-486
• /
• 2012

• Proceedings of the Korea Society for Energy Engineering kosee Conference
• /
• 2004.11a
• /
• pp.257-262
• /
• 2004

• 한국전산유체공학회:학술대회논문집
• /
• 2011.05a
• /
• pp.117-123
• /
• 2011

The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash memory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10 $^{\circ}C$ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is con finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9 $^{\circ}C$ lower than a multilayer structure of vertical type.