• The Magazine of the IEIE
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• v.29 no.9
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• pp.18-30
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• 2002

Wireless communication systems will be one of the biggest drivers of semiconductor products over the next decade. Global Positioning System (GPS) and Blue-tooth, HomeRF, and Wireless-LNA system are just a few of RF-module candidate awaiting integration into next generation mobile phone. Motivated by the generation mobile phone. Motivated by the growing needs for low-cost and multi-band/multi-function single chip wireless transceivers, CMOS technology has been recognized as a most promising candidate for the implementation of the future wireless communication systems. This paper presents recent developments in RF CMOS technology, which is classified into device technology and circuit technology and from them forecasts technology and from them forecasts technology trends in the near future.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.49-52
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• 2001

This paper presents product level considerations for multichip packaging as a cost effective alternative to single chip packaging in the design and manufacture of mobile telephony products. Important aspects include component functionality and complexity, acquisition and logistics costs, product modularity and integration. Multichip packaging offers unique solutions and significant system level cost savings in many applications including RF modules, digital matrix functions and product options such as security, data storage, voice recognition, etc.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.1-7
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• 2001

This paper presents product level considerations for multichip packaging as a cost effective alternative to single chip packaging in the design and manufacture of mobile telephony products. Important aspects include component functionality and complexity, acquisition and logistics costs, product modularity and integration. Multichip packaging offers unique solutions and significant system level cost savings in many applications including RF modules, digital matrix functions and product options such as security, data storage, voice recognition, etc.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.6
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• pp.906-911
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• 2001

In this paper, LPI(low probability of intercept) and AJ(anti jamming) performance of the chirped BPSK system are analyzed. In the chirp method the cyclostationary of the signal is eliminated, since the instantaneous frequency is varied randomly within the whole spread bandwidth. Therefore, chirp method is considered for good LPI system against DAM(delay-and-multiplier) or SC (squaring circuit) interceptor which detects the chip rate or carrier frequency. Longer chirp duration makes the LPI performance better. From the simulation results, the chirp method has better AJ performance than DS(direct sequence) system in the PBNJ(partial band noise jammer) channel. At the same JSR(jammer to signal power ratio) level, chirped BPSK system has more robust AJ performance against MTJ(multi-tone jammer) than PBNJ.

• ETRI Journal
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• v.22 no.4
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• pp.13-24
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• 2000

As more transistors are integrated onto bigger die, an on-chip multiprocessor will become a promising alternative to the superscalar microprocessor that dominates today's microprocessor marketplace. This paper describes key parts of a new on-chip multiprocessor, called Raptor, which is composed of four 2-way superscalar processor cores and one graphic co-processor. To obtain performance characteristics of Raptor, a program-driven simulator and its programming environment were developed. The simulation results showed that Raptor can exploit thread level parallelism effectively and offer a promising architecture for future on-chip multi-processor designs.

• ETRI Journal
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• v.36 no.2
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• pp.293-300
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• 2014

As the system-on-chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12B
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• pp.1637-1647
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• 2001

Multi-Code CDMA (MC-CDMA) can not only be integrated easily with a conventional system, but also achieve good spectral efficiency and high processing gain. However, it suffers from high value of peak-to-average power ratio (PAPR). In this paper, we propose the Multi-Phase CDMA (MP-CDMA) system that can provide variable rate service and is not susceptible to the non-linear characteristics of amplifier. The clipping is introduced between at the output of multi-code modulator and at the input of MPSK modulator in order to improve the performance of MPSK chip demodulator and reduce the system complexity, The system performances are compared for the different Number of codes and different clipping levels, respectively. The optimum clipping level is also evaluated for the different number of codes in both, AWGN and frequency flat fading channel.

• The Journal of Korea Robotics Society
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• v.4 no.1
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• pp.1-9
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• 2009

Radio Frequency Identification (RFID) is an automatic identification method. Information such as identification, logistics history, and specification of products are written and stored into the memory of RFID tags (that is, transponders), and retrieved through RF communication between RFID reader device and RFID tags. RFID systems have been applied to many fields of transportation, industry, logistics, environment, etc in order to improve business efficiency and reduce maintenance cost as well. Recently, some research results are announced in which RFID devices are combined with other sensors for mobile robot localization. In this paper, design of multi-protocol baseband for RFID reader device is proposed, and the baseband modem is implemented into SoC (System On a Chip). The baseband modem SoC for multi-protocol RFID reader is composed of several IP (Intellectual Property) blocks such as multi-protocol blocks, CPU, UART(Universal Asynchronous Receiver and Transmitter), memory, etc. As a result, the SoC implemented with FPGA(Field Programmable Gate Array) is applied to real product. It is shown that the size of RFID Reader module designed with the FPGA becomes smaller, and the SoC chip price for the same function becomes cheap. In addition, operation performance could be the same or better than that of the product with no SoC applied.

• Journal of Biomedical Engineering Research
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• v.22 no.3
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• pp.285-291
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• 2001

In this paper, we designed two preprocessing adaptive filter - high pass filter and notch filter - using FPGA. For minimizing the calculation load of multi-channel and high-resolution ECG system, we utilize FPGA rather than digital signal processing chip. To implement the designed filters in FPGA, we utilize FPGA design tool(Altera corporation, MAX-PLUS II) and CSE database as test data. In order to evaluate the performance in terms of processing time, we compared the designed filters with the digital filters implemented by ADSP21061(Analog Devices). As a result, the filters implemented by FPGA showed better performance than the filters based on ADSP21061. As a consequence of examination, we conclude that FPGA is a useful solution in multi-channel and high-resolution signal processing.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.154-156
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• 2006

A few ten mW white LED can substitute for the indicator light source and it is required to study several watt multi-chip semiconductor light sources in order to replace the light sources for general illumination such as incandescent lights and fluorescent lanes. Since the optical technology used for several mW white LED light source uses only 30% to 52% of the light it is required to develop the design technology of optical system and lens to improve the efficiency more than 80% for insuring the high power of white LED. In this paper, we designed and fabricated new structure reflector to increase the efficiency and is easy to make high power multi-chip LED lamp.