• Journal of KIISE:Computer Systems and Theory
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• v.26 no.4
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• pp.406-419
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• 1999

RSA와 같은 공개키 암호시스템(public-key cryptography system)에서는 512 비트 또는 그 이상 큰수의 모듈러 곱셈 연산을 수행하여야한다. 본 논문에서는 Montgomery 알고리즘을 이용하여 모듈러 곱셈을 수행하는 두 가지의 고정-크기 선형 시스톨릭 어레이를 설계하고 분석한다. 제안된 임의의 고정-크기 선형 시스톨릭 어레이와 파이프라인된 고정-크기 선형 시스톨릭 어레이는 최적의 문제-크기 선형 시스톨릭 어레이로부터 LPGS(Locally Parallel Globally Sequential)분할방법을 적용하여 설계한다. VHDL 시뮬레이션 결과, 밴드이 크기를 4로 하여 분할 시 문제-크기 어레이와 비교하면 수행시간의 지연이 없었으며,어레이의 크기도 1/4로 줄일 수 있었다. 제안된 시스톨릭 어레이는 크기에 제한을 갖는 스마트카드 등에 이용될수 있을 것이다.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.809-812
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• 2002

본 논문은 RSA 암호시스템에서 고속 모듈러 곱셈을 위한 최적화된 시스톨릭 어레이의 설계를 제안한다. 제안된 방법에서는 미리 계산된 가산결과를 사용하여 개선된 몽고메리 모듈러 곱셈 알고리듬을 제안하고, 고속 모듈러 곱셈을 위한 새로운 구조의 시스톨릭 어레이를 설계한다. 미리 계산된 가산결과를 얻기 위해 CLA(Carry Look-ahead Adder)를 사용하였으며, 이 가산기는 덧셈연산에 있어서 캐리전달 지연이 제거되므로 연산 속도를 향상 시킬 수 있다. 제안된 시스톨릭 구조는VHDL(VHSlC Hardware Description Language)을 사용하여 동작적 수준을 기술하였고, Ultra 10 Workstation 상에서 $Synopsys^{TM}$ 툴을 사용하여 합성 및 시뮬레이션을 수행하였다. 또한, FPGA 구현을 위하여 Altera MaxplusII를 사용하여 타이밍 시뮬레이션을 수행하였고, 실험을 통하여 제안한 방법을 효율성을 확인하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• The KIPS Transactions:PartA
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• v.14A no.2
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• pp.107-116
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• 2007

In this paper, we present a method on the construction of multiple-valued circuits using Reed-Muller Expansions(RME). First, we discussed the input output interconnection of multiple valued function using Perfect Shuffle techniques and Kronecker product and designed the basic cells of performing the transform matrix and the reverse transform matrix of multiple valued RME using addition circuit and multiplication circuit of GF(4). Using these basic cells and the input-output interconnection technique based on Perfect Shuffle and Kronecker product, we implemented the multiple valued logic circuit based on RME. The proposed design method of multiple valued RME is simple and very efficient to reduce addition circuits and multiplication circuits as compared with other methods for same function because of using matrix transform based on modular structures. The proposed design method of multiple valued logic circuits is simple and regular for wire routing and possess the properties of concurrency and modularity of array.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.281-286
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• 2002

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.613-623
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• 2011

In this paper, we present a method on the construction of quinternary logic circuits using Perfect shuffle. First, we discussed the input-output interconnection of quinternary logic function using Perfect Shuffle techniques and Kronecker product, and designed the basic cells of performing the transform matrix and the reverse transform matrix of quinternary Reed-Muller expansions(QRME) using addition circuit and multiplication circuit of GF(5). Using these basic cells and the input-output interconnection technique based on Perfect Shuffle and Kronecker product, we implemented the quinternary logic circuit based on QRME. The proposed design method of QRME is simple and very efficient to reduce addition circuits and multiplication circuits as compared with other methods for same logic function because of using matrix transform based on modular structures. The proposed design method of quinternary logic circuits is simple and regular for wire routing and possess the properties of concurrency and modularity of array.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.2
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• pp.159-164
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• 2004

This paper proposes a new digital filter implementation which adopts an identical structure at both behavioral and logic level in top-down design. This methodology is based on the observation that multiplication is a form of convolution and carrying, and therefore multiplication is implemented with the same structure as that of a convolution in a recursive manner at the logic level. In order to demonstrate a recursive structure-based FIR digital filter, we select L-tap transposed and systolic FIR filters, and implement them to have a single structure. The proposed filter design becomes regular and modular because of the recursive adoption of a single structure for convolutions, and is very compact in that it needs only two 1-bit I/O ports in addition to significant improvement on hardware complexity without time penalty on the output sequence.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.3
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• pp.419-426
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• 2021

A high-performance elliptic curve cryptography processor (HP-ECCP) was designed to support five field sizes of 192, 224, 256, 384 and 521 bits over GF(p) defined in NIST FIPS 186-2, and it provides eight modes of arithmetic operations including ECPSM, ECPA, ECPD, MA, MS, MM, MI and MD. In order to make the HP-ECCP resistant to side-channel attacks, a modified left-to-right binary algorithm was used, in which point addition and point doubling operations are uniformly performed regardless of the Hamming weight of private key used for ECPSM. In addition, Karatsuba-Ofman multiplication algorithm (KOMA), Lazy reduction and Nikhilam division algorithms were adopted for designing high-performance modular multiplier that is the core arithmetic block for elliptic curve point operations. The HP-ECCP synthesized using a 180-nm CMOS cell library occupied 620,846 gate equivalents with a clock frequency of 67 MHz, and it was evaluated that an ECPSM with a field size of 256 bits can be computed 2,200 times per second.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.7 s.349
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• pp.115-121
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• 2006

The efficiency of the multiplier largely depends on the representation of finite filed elements such as normal basis, polynomial basis, dual basis, and redundant representation, and so on. In particular, the redundant representation is attractive since it can simply implement squaring and modular reduction. In this paper, we propose an efficient bit-parallel multiplier for GF(2m) defined by an irreducible all-one polynomial using a redundant representation. We modify the well-known multiplication method which was proposed by Karatsuba to improve the efficiency of the proposed bit-parallel multiplier. As a result, the proposed multiplier has a lower space complexity compared to the previously known multipliers using all-one polynomials. On the other hand, its time complexity is similar to the previously proposed ones.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.6
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• pp.29-39
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• 2007

RSA is one of the most popular public-key crypto-system in various applications. This paper addresses a high-speed RSA crypto-processor with modified radix-4 modular multiplication algorithm and Chinese Remainder Theorem(CRT) using Carry Save Adder(CSA). Our design takes 0.84M clock cycles for a 1024-bit modular exponentiation and 0.25M cycles for a 512-bit exponentiations. With 0.18um standard cell library, the processor achieves 365Kbps for a 1024-bit exponentiation and 1,233Kbps for two 512-bit exponentiations at a 300MHz clock rate.