• Proceedings of the IEEK Conference
• /
• 2003.11b
• /
• pp.167-170
• /
• 2003

In this paper, a design and experiment of PCI Express Core verification Model is described. The model targeting Endpoint core verification is designed by using newly-emerging SystemC which is a system design language based on a new C++ class library and simulation engine. In the verification model, we developed a SystemC Host System model which act as a Root Complex and Device Driver dedicated to the PCI Express Endpoint RTL Core. The test of Host System Model is guided by scenarios which implements and acts point of Device Driver and Root Complex and shows the result of simulation. Also, We present the full structure of verification model and Host model.

• Speech Sciences
• /
• v.14 no.2
• /
• pp.127-135
• /
• 2007

Feature vectors of speech are generally extracted from whole frequency domain. The inherent character of a speaker is located in the low band or high band frequency. However, if the speech is corrupted by narrowband noise with concentrated energy, speaker verification performance is reduced as the individual characteristic is removed. In this paper, we propose a PCA Covariance Model based on the multiband to extract the robust feature vectors against the narrowband noise. First, we divide the overall frequency band into several subbands. Second, the correlation of feature vectors extracted independently from each subband is removed by PCA. The distance obtained from each subband has different distribution. To normalize against the different distribution, we moved the value into the normalized distribution through the mapping function. Finally, the represented value applying the weighting function is used for speaker verification. In the experiments, the proposed method shows better performance of the speaker verification and reduces the computation.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.19 no.10
• /
• pp.410-417
• /
• 2018

System design errors are more likely to occur in modern systems because of their steadily increasing size and complexity. Failures due to system design errors can cause safety-related accidents in the system, resulting in extensive damage to people and property. Therefore, international standards organizations, such as the U.S. Department of Defense and the International Electrotechnical Commission, have established international safety standards to ensure system safety, and recommend that system design and safety activities should be integrated. Recently, the safety of a system has been verified by modeling through a model-based system design. On the other hand, system design and safety activities have not been integrated because the model for system design and the failure model for safety analysis and verification were developed using different modeling language platforms. Furthermore, studies using UML or SysML-based failure models for deriving safety requirements have shown that these models have limited applicability to safety analysis and verification. To solve this problem, it is essential to extend the existing methods for failure model implementation. First, an improved SysML-based failure model capable of integrating system design and safety verification activities should be produced. Next, this model should help verify whether the safety requirements derived via the failure model are reflected properly in the system design. Therefore, this paper presents the concept and method of developing a SysML-based failure model for an automotive system. In addition, the failure model was simulated to verify the safety of the automotive system. The results show that the improved SysML-based failure model can support the integration of system design and safety verification activities.

• Journal of Information Technology Services
• /
• v.10 no.3
• /
• pp.189-201
• /
• 2011

Feature models are widely used to model commonalities and variabilities among products during software product line development. Feature configurations are generated by selecting the features to be included in individual products. Automated tools to identify errors or inconsistencies in the feature models and configurations are essential to successful software product line engineering. This paper proposes a verification technique and tool based on semantic web technologies such as OWL, SWRL and Protege API. This approach checks the feature model and configuration based on predefined rules and provides information on existence of errors as well as the kinds of those errors. This approach is extensible due to ease of rule modification and may be easily applied to other environments because semantic web technologies can be easily integrated with other programming environments. This paper demonstrates how various semantic web-related technologies can support automatic verification of one kind of software development artifact, the feature model.

• IEIE Transactions on Smart Processing and Computing
• /
• v.2 no.5
• /
• pp.277-281
• /
• 2013

Modern speaker verification systems based on support vector machines (SVMs) use Gaussian mixture model (GMM) supervectors as their input feature vectors, and the maximum a posteriori (MAP) adaptation is a conventional method for generating speaker-dependent GMMs by adapting a universal background model (UBM). MAP adaptation requires the appropriate amount of input utterance due to the number of model parameters to be estimated. On the other hand, with limited utterances, unreliable MAP adaptation can be performed, which causes adaptation noise even though the Bayesian priors used in the MAP adaptation smooth the movements between the UBM and speaker dependent GMMs. This paper proposes a sparse MAP adaptation method, which is known to perform well in the automatic speech recognition area. By introducing sparse MAP adaptation to the GMM-SVM-based speaker verification system, the adaptation noise can be mitigated effectively. The proposed method utilizes the L0 norm as a regularizer to induce sparsity. The experimental results on the TIMIT database showed that the sparse MAP-based GMM-SVM speaker verification system yields a 42.6% relative reduction in the equal error rate with few additional computations.

• Journal of the Korean Society for Precision Engineering
• /
• v.17 no.2
• /
• pp.114-120
• /
• 2000

Fossil power plant availability is significantly affected by gradual degradations of equipment as operation of the plant continues. It is quite important to determine whether or not to replace some equipment and when to replace the equipment. Performance calculation and analysis can provide the information. Robustness in the performance calculation can be increased by using verification ＆ validation of measured input data. We suggest new algorithm in which estimation relation for validated measurement can be obtained using correlation between measurements. Input estimation model is obtained using design data and acceptance measurement data of domestic 16 fossil power plant. The model consists of finding mostly correlated state variable in plant state and mapping relation based on the model and current state of power plant.

• ETRI Journal
• /
• v.44 no.4
• /
• pp.599-612
• /
• 2022

This study focuses on improving a word embedding model to enhance the performance of downstream tasks, such as those of dialog systems. To improve traditional word embedding models, such as skip-gram, it is critical to refine the word features and expand the context model. In this paper, we approach the word model from the perspective of subword embedding and attempt to extend the context model by integrating various sentence models. Our proposed sentence model is a subword-based skip-thought model that integrates self-attention and relative position encoding techniques. We also propose a clustering-based dialog model for downstream task verification and evaluate its relationship with the sentence-model-based subword embedding technique. The proposed subword embedding method produces better results than previous methods in evaluating word and sentence similarity. In addition, the downstream task verification, a clustering-based dialog system, demonstrates an improvement of up to 4.86% over the results of FastText in previous research.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.755-758
• /
• 1998

As the performance of microprocessor improves, the design complexity grows exponentially. Therefor, it is very important to make the bug-free model as early as possible in a design life-cycle. This paper describes the simulation-based functional verification methodology for the RTL level description model. It is performed by multi-stage verification methods using extensive hand-generated self-checking tests supplemented with random tests. This approach is opplied to the functional verification of the GPU processor of Raptor and various bugs are detected.

• Proceedings of the IEEK Conference
• /
• summer
• /
• pp.281-284
• /
• 2004

In this paper, a verification method and model for a PCI-Express device are described. PCI-Express technology is one of new I/O interconnection technologies which is intended to replace conventional PCI based technology, and is introduced by PCI-SIG in 2002. For a fast prototyping, a verification suite which includes a behavioral model and stimuli is needed before actual design is finished. And also it should be simple in structure and accurate enough to verify the design. In this paper, an Early Verification Suite (EVS) which complies with PCI-Express protocol is developed and tested.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.8
• /
• pp.1435-1442
• /
• 2006

The ideal method of safety evaluation is to verify results of execution against all possible operations within operating system, but it is impossible. However, the formal method can theoretically prove the safety on actual logic of operating system. Therefore we explain the contents of the art of the safety verification of security kernel, and make a comparative study of various standardized formal verification tools. And then we assigned PVS(Prototype Verification system) of SRI(Stanford Research Institute) to verify the safety of a modified BLP(Bell & LaPadula) model, the core access control model of multi-lavel based security kernel. Finally, we describe formal specification of the revised BLP model using the PVS, and evaluate the safety of the model by inspecting the specification of the PVS.