• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.5
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• pp.963-969
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• 2006

In this study, we designed a digital fuzzy logic controller based on FPGA and microprocessor for MPPT of the solar power generation system. A fuzzy algorithm to control the power tracking function of a boost converter has been built into the FPGA, and applied to the small scaled solar power generation system. The embodied controller showed a stable operation characteristic with the small output voltage ripple for the intensity change of solar radiation. This result proves that the implementation of the power tracking controller using FPGA is an effective way compared to the existing one using microprocessors.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.803-805
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• 1993

This paper describes the development of a digital multifunction controller for the protection, measurement and control of the high voltage customer switchboard. The magnitude of the fundamental component is estimated using a simple filter based on cross-correlation with a heptagonal wave. The characteristics of flexible relay functions such as adjustable pickup and time-dial settings, various time-magnitude curve and directional capability including measurement functions are presented. The controller implementation is carried out on two microprocessors for real time operation.

• Proceedings of the KIEE Conference
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• 1985.07a
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• pp.257-261
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• 1985

This paper deals with the personal computer based design for the sequential machines. Most part of sequential machine design have been implemented by using general purpose microprocessors in order to obtain the specific unctions required for their system. But, they have some difficulties in design stages. Knowledge of systems design method and high technology are basically applied to all the design stages.. Therefore ready made microcomputer system for personal use, personal computer, can be transformed to sequential machines by using the corresponding softwares and built-in personal computer input/output ports. Following the state transition diagram or table, we can obtain the ROM type of sequential machines directly and need not to design input/output interface except actuators and samplers because of capability of personal computer. Our main purpose of this design method are quick, flexible, reliable, modifiable circuit design of the sequential machines. In this paper, we use APPLE-II plus personal computer as target machine.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2005.11a
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• pp.143-146
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• 2005

In modern automotive control modules, mechanical failures of surface mounted electronic components such as microprocessors, crystals, capacitors, transformers, inductors, and ball grid array packages, etc., are mai or roadblocks to design cycle time and product reliability. This paper presents a general methodology of failure analysis and fatigue prediction of these electronic components under automotive vibration environments. Mechanical performance of these packages is studied through finite element modeling approach fur given vibration environments in automotive application. Using the results of vibration simulation, fatigue lift is predicted based on cumulative damage analysis and material durability information. Detailed model of solder/lead joints is built to correlate the system level model and obtain solder strains/stresses. The primary focus in this paper is on surface-mount interconnect fatigue failures and the critical component selected for this analysis is 80 pin plastic leaded microprocessor.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.36 no.1
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• pp.78-85
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• 2013

Since the basic built-in-test, prognostic health management (PHM) has evolved into more sophisticated and complex systems with advanced warning and failure detection devices. Aerospace and military systems, manufacturing equipment, structural monitoring, automotive electronic systems and telecommunication systems are examples of fields in which PHM has been fully utilized. Nowadays, the automotive electronic system has become more sophisticated and increasingly dependent on accurate sensors and reliable microprocessors to perform vehicle control functions which help to detect faults and to predict the remaining useful life of automotive parts. As the complication of automotive system increases, the need for intelligent PHM becomes more significant. Given enormous potential to be developed lays ahead, this paper presents findings and discussions on the trends of automotive PHM research with the expectation to offer opportunity for further improving the current technologies and methods to be applied into more advanced applications.

• Proceedings of the KSR Conference
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• 1999.11a
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• pp.280-287
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• 1999

An automatic train operation(ATO) system executes the operation of constant speed travelling and fixed point parking by using microprocessors instead of drivers manual operation. This paper describes the mathematical model for the train considering unknown disturbances which consist of start resistance, travelling resistance, slope resistance, curve resistance, and so on. The speed controller of ATO system is designed by considering the disturbances. The simulation is executed to verify the speed control and fixed point parking performance and to compare its performance with that of a PID-type ATO control system under disturbances. Simulation results show that the control performance of gain scheduled control scheme fur ATO system is better than that of the conventional PID controller.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.04a
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• pp.119-124
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• 1986

This paper describes the development of the KORNET that may be regarded as the latest public packet-swiched computer communication network. The KORNET project included the development of the network management center (NMC), a network concentrator. For the KORNET we use the virtual circuit(VC) method, a distributed adaptive routing algorithm, and a dynamic buffer management algorithm. The NMC acts as a nerve center of the network, performing such function as network monitoring, subscriber and network management and routing management, etc. As for the NNP and NC hardware, we have implemented them with the 16-bit multitask/multiprocessor technology using MC68000 microprocessors. Softwares have been developed using C language is required for real time processing. All the network protocols we have developed comply completely with the latest CCITT recommendations including X.25, X,3 , X.28 and X.29.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.45-52
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• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.156-163
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• 2006

The objective of this paper is to evaluate the performance of an operating system for embedded devices to that of the commercially available Windows platform. Analysis includes benchmarking the operating systems using a 'typical' PC workload, as well as identifying low-level areas in which the updated OS is limiting or enhancing the system performance. The primary benchmarking suites selected for this paper are 'WinStone' and 'HBench', with the former providing an application-based suite of tests and the latter providing the most direct means for isolating operating system effects on the system. We have demonstrated in a case study for embedded microprocessors, and evaluated a Windows platform at a low-level test as well as an application level using a benchmarking suite.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.