• Journal of IKEEE
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• v.19 no.2
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• pp.232-236
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• 2015

Super-junction trench MOSFET (SJ TMOSFET) devices are well known for lower specific on-resistance and high breakdown voltage (BV). For a conventional power MOSFET (metal-oxide semiconductor field-effect transistor) such as trench double-diffused MOSFET (TDMOSFET), there is a tradeoff relationship between specific on-state resistance and breakdown voltage. In order to overcome the tradeoff relationship, a SJ TMOSFET structure is suggested, but sensing the temperature distribution of TMOSFET is very important in the application since heat is generated in the junction area affecting TMOSFET. In this paper, analyzing the temperature characteristics for different number bonding for SJ TMOSFET with an embedded temperature sensor is carried out after designing the diode temperature sensor at the surface of SJ TMOSFET for the class of 100 V and 100 A for a BLDC motor.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.2
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• pp.181-184
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• 2017

This study analyzes the turn-on and turn-off transients of a metal-oxide-semiconductor field-effect transistor (MOSFET) with high-switching frequency systems. In these systems, the voltage distortion becomes serious at the output terminal of a Vienna rectifier by the turn-off delay of the MOSFET. The current has low-order harmonics through this voltage distortion. This paper describes the transient of the turn-off that causes the voltage distortion. The algorithm for reducing the sixth harmonic using a proportional-resonance controller is proposed to improve the current distortion without complex calculation for compensation. The reduction of the current distortion by high-switching frequency is verified by experiment with the 2.5-kW prototype Vienna rectifier.

• Proceedings of the KIEE Conference
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• 2002.11a
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• pp.159-160
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• 2002

본 논문에서는 반도체 응용부문 중 그 활용도가 높은 MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor)의 새로운 구조를 제안하였다. 제안한 소자를 가지고 전자회로의 구성할 때 인접 디바이스들과 연계되어 발생되는 래치 업(latch-up)을 근본적으로 제거하고, 개별소자의 완전한 절연을 실현하였으며 누설전류 또한 제거된다. 이는 SOI기판 위에 벌크실리콘 공정을 이용하여 구현된다. 즉, 소자 양옆의 트랜치 웰(Trench-well)과 SOI 기판의 절연층으로 소자의 독립성을 지켜준다. 또한 게이트 절연층을 트랜치 구조로 기존 MOS구조의 채널 부분에 위치시키고 드레인과 소스를 위치시켜 자연적으로 자기정렬이 되어진다. 이와 같은 과정으로 게이트-소스, 게이트-드레인 기생 커패시터의 효과를 현저히 줄일 수 있다.

• ETRI Journal
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• v.43 no.4
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• pp.728-745
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• 2021

Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.

• ETRI Journal
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• v.44 no.3
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• pp.491-503
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• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.284-288
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• 2013

Power MOSFETs(Metal Oxide Semiconductor Field Effect Transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. We have experimental results and explanations on the doping profile dependence of the electrical behavior of the vertical MOSFET. The device is fabricated as $8.25{\mu}m$ cell pitch and $4.25{\mu}m$ gate width. The performances of device with various p base doping concentration are compared at Vth from 1.77 V to 4.13 V. Also the effect of the cell structure on the on-resistance and breakdown voltage of the device are analyzed. The simulation results suggest that the device optimized for various applications can be further optimized at power device.

• Journal of Sensor Science and Technology
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• v.19 no.4
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• pp.306-312
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• 2010

We have detected deoxynivalenol(DON) using a metal-oxide-semiconductor field-effect-transistor(MOSFET)-based biosensor. The MOSFET-based biosensor is fabricated by a standard complementary metal-oxide-semiconductor(CMOS) process, and the biosensor's electrical characteristics were investigated. The output of the sensor was stabilized by employing a reference electrode that applies a fixed bias to the gate. Au which has a chemical affinity for thiol was used as the gate metal to immobilize a self-assembled monolayer(SAM) made of 16-mercaptohexadecanoic acid(MHDA). The SAM was used to immobilize anti-deoxynivalenol antibody. The carboxyl group of the SAM was bound to the anti- deoxynivalenol antibody. Anti-deoxynivalenol antibody and deoxynivalenol were bound by an antigen-antibody reaction. In this study, it is confirmed that the MOSFET-based biosensor can detect deoxynivalenol at concentrations as low as 0.1 ${\mu}g$/ml. The measurements were performed in phosphate buffered saline(PBS; pH 7.4) solution. To verify the interaction among the SAM, antibody, and antigen, surface plasmon resonance(SPR) measurements were performed.

• Journal of Sensor Science and Technology
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• v.14 no.3
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• pp.137-143
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• 2005

Research in the field of biosensor has enormously increased over the recent years. The metal-oxide semiconductor field effect transistor (MOSFET) type protein sensor offers a lot of potential advantages such as small size and weight, the possibility of automatic packaging at wafer level, on-chip integration of biosensor arrays, and the label-free molecular detection. We fabricated MOSFET protein sensor and proposed the gold-black electrode as the gate metal to improve the response. The experimental results showed that the output voltage of MOSFET protein sensor was varied by concentration of albumin proteins and the gold-black gate increased the response up to maximum 13 % because it has the larger surface area than that of planar-gold gate. It means that the expanded gate allows a larger number of ligands on same area, and makes the more albumin proteins adsorbed on gate receptor.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.302-305
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• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.281.2-281.2
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• 2016

Two-dimensional van der Waals (2D vdWs) materials have been extensively studied for future electronics and materials sciences due to their unique properties. Among them, black phosphorous (BP) has shown infinite potential for various device applications because of its high mobility and direct narrow band gap (~0.3 eV). In this work, we demonstrate a few-nm thick BP-based nonvolatile memory devices with an well-known poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] ferroelectric polymer gate insulator. Our BP ferroelectric memory devices show the highest linear mobility value of $1159cm^2/Vs$ with a $10^3$ on/off current ratio in our knowledge. Moreover, we successfully fabricate the ferroelectric complementary metal-oxide-semiconductor (CMOS) memory inverter circuits, combined with an n-type $MoS_2$ nanosheet transistor. Our memory CMOS inverter circuits show clear memory properties with a high output voltage memory efficiency of 95%. We thus conclude that the results of our ferroelectric memory devices exhibit promising perspectives for the future of 2D nanoelectronics and material science. More and advanced details will be discussed in the meeting.