• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.147-152
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• 2016

In this study, we fabricated Ag-based electrochemical metallization memory devices which is also called conductive-bridge random-access memory (CBRAM) in order to investigate the resistive switching behavior depending on the bottom electrode (BE). RRAM cells of two different layer configurations having $Ag/Si_3N_4/TiN$ and $Ag/Si_3N_4/p^+$ Si are studied for metal-insulator-metal (MIM) and metal-insulator-silicon (MIS) structures, respectively. Switching voltages including forming/set/reset are lower for MIM than for MIS structure. It is found that the workfunction different affects the performances.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.83-83
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• 2008

Metal-oxide-silicon-on-insulator (MOSOI) structures were fabricated to study the effect caused by reactive ion etching (RIE) and sacrificial oxidation process on silicon-on-insulator (SOI) layer. The MOSOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching treatment. The measured C-V curves were compared to the numerical results from 2-dimensional (2-D) simulations. The measurements revealed that the profile of C-V curves significantly changes depending on the SOI surface condition of the MOSOI capacitors. The shift in the measured C-V curves, due to the difference of the fixed oxide charge ($Q_f$), together with the numerical simulation analysis and atomic force microscopy (AFM) analysis, allowed extracting the fixed oxide charges ($Q_f$) in the structures as well as 2-D carrier distribution profiles.

• 한국전기전자재료학회논문지
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• 제17권3호
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• pp.283-288
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• 2004

We have fabricated MIM capacitors for MMIC applications, with capacitances as high as 600pF/$\textrm{mm}^2$ and excellent electrical properties of the insulator layer. Silicon nitride thin film is the desirable material for MMIC capacitor fabrication. Standard MIM capacitance in MMIC is 300pF/$\textrm{mm}^2$ with an insulator layer thickness of more than 2000$\AA$. However, capacitors with thin insulator layers have breakdown voltages as low as 20V. We have deposited insulator layers by PECVD in our MIM structure with an air bridge between the top metal and the contact pad. The PECVD process was optimized for fabricating the desired capacitors to be used in MMIC. Silicon nitride(Si$_{x}$N$_{y}$) thin films of about 1000$\AA$ thick show capacitances of about 600pF/$\textrm{mm}^2$, and breakdown voltages above 70V at 100nA.A.A.

• 통합자연과학논문집
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• 제3권1호
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• pp.7-18
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• 2010

Ethylene-bridged silsesquioxane resins were synthesized from two monomers: 1,2-bis(trimethoxysilyl)ethane and methyltrimethoxysilane. The silsesquioxane thin films were spin-coated from the copolymerized resins on silicon wafer. Metal insulator metal (MIM), metal insulator semiconductor (MIS) devices were utilized to investigate the electrical properties of the copolymerized thin films. As the films were inserted as gate insulator in the OTFT devices, the field effect mobilitites were evaluated by employing Poly(3-hexylthiophene) (P3HT) as organic semiconductor, which shows that their dielectric properties and mobility values are dependent on the molecular structures and Si-OH concentration involving in the films.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1085-1088
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• 2003

In this work, we fabricated a gas-sensing device based on porous silicon(PS), and its I-V and C-V properties were investigated for sensing alcohol vapor. The structure of the sensor consists of thin Au/Oxidized porous silicon/porous silicon/Silicon/Al, where the silicon substrate is etched anisotropically to be prepared into a membrane shape. As the result, I-V curves showed typical tunneling property, and C-V curves were shaped like those of a MIS (metal-insulator- semiconductor) capacitor, where the capacitance in accumulation was increased with alcohol vapor concentration.

• ETRI Journal
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• 제17권4호
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• 한국전기전자재료학회논문지
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• 제28권11호
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• pp.698-703
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• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• 전기전자학회논문지
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• 제22권3호
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• pp.706-711
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• 2018

본 논문에서는 플라즈마 화학기상증착 (plasma enhanced chemical vapor deposition, PECVD) 방식을 이용한 산질화규소(Silicon oxynitride, SiON) 절연체를 이용하여 4H-SiC metal-oxide-semiconductor (MOS) 소자를 제작하고 특성 분석을 수행하였다. 제작된 소자는 금속 증착 후 열처리 과정 (post metallization annealing, PMA)을 통하여 트랩 밀도가 크게 감소하는 것을 확인하였으며, 특히 $500^{\circ}C$의 forming gas 분위기에서 열처리 된 소자의 경우 매우 뛰어난 MOS 특성을 나타내었다. 본 연구를 통하여 4H-SiC MOS 구조를 위한 대체 게이트 절연체로써 PECVD SiON의 활용 가능성을 확인 할 수 있었다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.951-952
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• 2009

The long way toward new silicon technology, processed at very low temperature on any substrate, is described. The technology is based on CMIS (Complementary Metal Insulator Semiconductor) structure that shown its efficiency with known CMOS electronics. Present performance of this new technology is discussed through electrical parameters and reliability of transistors.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.342-342
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• 2011

산화막은 반도체 공정 중 가장 핵심적이며 기본적인 물질이다. 반도체 소자에서 내부의 캐리어들의 이동을 막고 전기를 절연시켜주는 절연체로서 역할을 하게 된다. 실제로 제작된 산화막에서는 dangling bond 혹은 내부에 축적되는 charge들의 의해 leakage가 생기게 되고 그에 따라 산화막의 특성은 저하되게 된다. 내부에서 특성을 저하시키는 defect을 감소시키기 위해 Plasma Treatment에 따른 특성변화를 관찰하였다. 본 연구에서는 최적화 시킨 Flexible TFT제작을 위해 저온에서 Silicon Oxide로 형성한 Gate Insulator에 각각 N2O, H2, NH3가스를 주입 후 Plasma처리를 하였다. 특성화 시킨 Gate Insulator를 이용하여 MIS(Metal-Insulator-Semiconductor)구조를 제작 후 C-V curve특성변화, Dit의 감소, Stress bias에 따른 stability를 확인 하였다.