• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.223-229
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• 2017

This paper analyzes the effect of a dual-metal-gate structure on the electrical characteristics of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors. These structures have two gate metals of different work function values (${\Phi}$), with the metal of higher ${\Phi}$ in the source-side gate, and the metal of lower ${\Phi}$ in the drain-side gate. As a result of the different ${\Phi}$ values of the gate metals in this structure, both the electric field and electron velocity in the channel become better distributed. For this reason, the transconductance, current collapse phenomenon, breakdown voltage, and radio frequency characteristics are improved. In this work, the devices were designed and analyzed using a 2D technology computer-aided design simulation tool.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.543-548
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• 2014

In this paper, the dielectric relaxation and reliability of high capacitance density metal-insulator-metal (MIM) capacitors using $Al_2O_3-HfO_2-Al_2O_3$ and $SiO_2-HfO_2-SiO_2$ sandwiched structure under constant voltage stress (CVS) are characterized. These results indicate that although the multilayer MIM capacitor provides high capacitance density and low dissipation factor at room temperature, it induces greater dielectric relaxation level (in ppm). It is also shown that dielectric relaxation increases and leakage current decreases as functions of stress time under CVS, because of the charge trapping effect in the high-k dielectric.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.112-112
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• 2009

Temperature dependence of the ferroelectric properties of poly(vinylidefluoride-trifluoroethylene) copolymer thin films are studied with various insulators such as $SrTa_2O_6$ and $La_2O_3$. Thin films of poly(vinylidene fluoridetrifluoroethylene) 75/25 copolymer were prepared by chemical solution deposition on p-Si substrate. Capacitance-voltage (C-V) and current density (J-V) behavior of the Au/P(VDF-TrFE)/Insulator/p-Si structures were studied at ($150-200\;^{\circ}C$) and dielectric constant of the each insulators were measured to be about 15 at $850\;^{\circ}C$ for 10 minutes. Memory window width at 5 V bias the MFIS(metal-ferroelectric-insulator-semiconductor) structure with as deposited films was about 0.5 V at high temperature ($200\;^{\circ}C$). And the memory window width increased as voltage increased from 1 V to 5 V.

• 전자공학회논문지 IE
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• v.43 no.2
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• pp.7-10
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• 2006

A GaN-based metal-insulator-semiconductor (MIS) structure has been fabricated by using $BaTa_2O_6$ instead of conventional oxide as insulator gate. The leakage current o) films are in order of $10^{-12}-10^{-13}A/cm^2$ for GaN on $Al_2O_3$(0001) substrate and in order of $10^{-6}-10^{-7}A/cm^2$ for GaN on GaAs(001) substrate. The leakage current of thses films is governed by space-charge-limited current over 45 MV/cm in case of GaN on $Al_2O_3$(0001) substrate and by Poole-Frenkel emission in case of GaN on GaAs(001).

• Journal of the Korean Chemical Society
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• v.40 no.3
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• pp.167-172
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• 1996

For the preparation of single-crystalline GaN film, heteroepitaxial growth on a sapphire substrate was carried out by halide vapor phase epitaxy(HVPE) method. The resulting GaN films showed n-type conductivity. The insulator type GaN film was made by doping with Zn(acceptor dopant), which showed emission peaks around 2.64 and 2.43 eV. The result of this study indicates that GaN can be obtained in an epitaxial structure of MIS(metal-insulator-semiconductor) junction. The observed data are regarded as fundamental in developing GaN epitaxial films for light emitting devices of hetero-structure type.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.5
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• pp.365-370
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• 2000

Schottky contacts on n-In$\_$0.53//Ga$\_$0.47//As have been made by metal deposition on substrates cooled to a temperature of 77K. The current-voltage and capacitance-voltage characteristics showed that the Schottky diodes formed at low temperature had a much improved barrier height compared to those formed at room temperature. The Schottky barrier height ø$\_$B/ was found to be increased from 0.2eV to 0.6eV with Ag metal. The saturation current density of the low temperature diode was about 4 orders smaller than for the room temperature diode. A current transport mechanism dominated by thermionic emission over the barrier for the low temperature diode was found from current-voltage-temperature measurement. Deep level transient spectroscopy studies exhibited a bulk electron trap at E$\_$c/-0.23eV. The low temperature process appears to reduce metal induced surface damage and may form an MIS (metal-insulator-semiconductor)-like structure at the interface.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1220-1224
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• 2007

The effects of plasma damages to the organic thin film transistor (OTFT) during the fabrication process are investigated; metal deposition process on the organic gate insulator by plasma sputtering mainly generates the process induced damages of bottom contact structured OTFTs. For this study, various deposition methods (thermal evaporation, plasma sputtering, and neutral beam based sputtering) and metals (gold and Indium-Tin Oxide) have been tested for their damage effects onto the Poly 4-vinylphenol(PVP) layer surface as an organic gate insulator. The surface damages are estimated by measuring surface energies and grain shapes of organic semiconductor on the gate insulator. Unlike thermal evaporation and neutral beam based sputtering, conventional plasma sputtering process induces serious damages onto the organic surface as increasing surface energy, decreasing grain sizes, and degrading TFT performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• Korean Journal of Materials Research
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• v.27 no.1
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• pp.48-52
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• 2017

In this study, we used I-V spectroscopy, photoconductivity (PC) yield and internal photoemission (IPE) yield using IPE spectroscopy to characterize the Schottky barrier heights (SBH) at insulator-semiconductor interfaces of Pt/$HfO_2$/p-type Si metal-insulator-semiconductor (MIS) capacitors. The leakage current characteristics of the MIS capacitor were analyzed according to the J-V and C-V curves. The leakage current behavior of the capacitors, which depends on the applied electric field, can be described using the Poole-Frenkel (P-F) emission, trap assisted tunneling (TAT), and direct tunneling (DT) models. The leakage current transport mechanism is controlled by the trap level energy depth of $HfO_2$. In order to further study the SBH and the electronic tunneling mechanism, the internal photoemission (IPE) yield was measured and analyzed. We obtained the SBH values of the Pt/$HfO_2$/p-type Si for use in Fowler plots in the square and cubic root IPE yield spectra curves. At the Pt/$HfO_2$/p-type Si interface, the SBH difference, which depends on the electrical potential, is related to (1) the work function (WF) difference and between the Pt and p-type Si and (2) the sub-gap defect state features (density and energy) in the given dielectric.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.342-342
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• 2011

산화막은 반도체 공정 중 가장 핵심적이며 기본적인 물질이다. 반도체 소자에서 내부의 캐리어들의 이동을 막고 전기를 절연시켜주는 절연체로서 역할을 하게 된다. 실제로 제작된 산화막에서는 dangling bond 혹은 내부에 축적되는 charge들의 의해 leakage가 생기게 되고 그에 따라 산화막의 특성은 저하되게 된다. 내부에서 특성을 저하시키는 defect을 감소시키기 위해 Plasma Treatment에 따른 특성변화를 관찰하였다. 본 연구에서는 최적화 시킨 Flexible TFT제작을 위해 저온에서 Silicon Oxide로 형성한 Gate Insulator에 각각 N2O, H2, NH3가스를 주입 후 Plasma처리를 하였다. 특성화 시킨 Gate Insulator를 이용하여 MIS(Metal-Insulator-Semiconductor)구조를 제작 후 C-V curve특성변화, Dit의 감소, Stress bias에 따른 stability를 확인 하였다.