• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.112-112
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• 2013

Well-defined surfaces of single-crystalline solid materials are starting points of self-organizationof nanostructures and chemical reactions controlled in nanoscale. Although highly ordered atomicarrangement can be obtained on semiconductor surfaces, they can be maintained only in vacuumand not in air or in aqueous environment. Since single-crystalline metal oxide surfaces arechemically stable and no further oxidation occurs, their atomic structures can be utilized fornanofabrication in liquid processes, nanoelectrochemistry and nanobiotechnology. Sapphire is oneof the most stable metal oxides and its crystalline quality is excellent, as can be applied to electronicdevices that require ultralow defect densities. We recently found that chemical phase separationoccurs on sapphire surfaces by annealing processes and the formed nanodomains exhibit specificproperties in air and in water [1,2]. In our experiments, highly selective and controllable adsorptionof various protein molecules is observed on the phase-separated surfaces though the materials andcrystallographic orientations are identical [3,4]. Planar lipid bilayers supported on thephase-separated sapphire surface also exhibit a specific formation site selectivity [5]. Chemicalnanodomains appear on other metal-oxide surfaces, such as well-ordered titania surfaces. Wedemonstrate that surface chemistry of the nanodomains can be characterized in aqueousenvironment using atomic force microscopy equipped with colloidal tips and then show adsorptionand desorption behaviors of various proteins on the phase-separated surfaces.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.79-79
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• 2003

최근 CMOS(Complementary Metal Oxide Semiconductor) 능동소자에 사용되는 MOS-FET (Metal Oxide Semiconductror Field Effect Transitror)의 전체적인 크기 감소추세에 따라 금속 전극과 반도체 사이의 절연층 두께 감소가 요구되고 있다. 현재 보편적으로 사용되고 있는 SiO$_2$층은 두께 감소에 따른 터널링 전류의 증가로 더 이상의 두께 감소를 기대하기 어려운 상태이다. 이러한 배경에서 최근 터널링 전류를 충분히 감소시키면서 요구되는 절연특성을 얻을 수 있는 새로운 고유전 물질 (high-k dielectric material)에 대한 연구가 이루어지고 있다. 현재까지 연구되어온 고유전 물질 중, 고유전 상수, 큰 밴드갭, Si과의 열적 안정성을 갖는 물질로 ZrO$_2$가 주목을 받고 있다. 본 연구에서는 Metal Organic Molecular Beam Epitaxy (MOMBE) 방법을 이용한 ZrO$_2$ 층의 성장조건 및 특성을 평가하고자 한다.

• Korean Journal of Materials Research
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• v.16 no.8
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• pp.503-510
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• 2006

The measurement of specific gases is based on the reversible conductivity change of sensing materials in semiconductor type gas sensors. For an application as gas sensors of high sensitivity, porous $SnO_2$ films have been fabricated by anodizing of pure Sn foil in oxalic acid and characteristics of anodic tin oxide films have been investigated. Pore diameter and distribution were dependent on process conditions such as electrolyte concentration, applied voltage, anodizing temperature, and time. Characteristics of anodic films were explained with current density-time curves.

• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.377-379
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• 1989

Very thin gate oxide(100-300A) MOS capacitor has been fabricated. The effect of series resistance must be calculated and the exact metal-semiconductor work function difference should be obtained to get the fixed oxide charge density exisiting in oxide. Dilute oxidation make sagy to control oxide thickness and reduce fixed oxide charge density. In case of dilute oxidation, fixed oxide charge density depends on oxidation time. If oxide is very thin, the annealing effect is ignored.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.463-463
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• 2012

ITRS (international technology roadmap for semiconductors)에 따르면 MOS(metal-oxide-semiconductor)의 CD (critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/$SiO_2$를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두된다고 보고하고 있다. 일반적으로 high-k dielectric를 식각시 anisotropic 한 식각 형상을 형성시키기 위해서 plasma를 이용한 RIE (reactive ion etching)를 사용하고 있지만 PIDs (plasma induced damages)의 하나인 PIED (plasma induced edge damage)의 발생이 문제가 되고 있다. PIED의 원인으로 plasma의 direct interaction을 발생시켜 gate oxide의 edge에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 high-k dielectric의 식각공정에 HDP (high density plasma)의 ICP (inductively coupled plasma) source를 이용한 원자층 식각 장비를 사용하여 PIED를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. One-monolayer 식각을 위한 1 cycle의 원자층 식각은 총 4 steps으로 구성 되어 있다. 첫 번째 step은 Langmuir isotherm에 의하여 표면에 highly reactant atoms이나 molecules을 chemically adsorption을 시킨다. 두 번째 step은 purge 시킨다. 세 번째 step은 ion source를 이용하여 발생시킨 Ar low energetic beam으로 표면에 chemically adsorbed compounds를 desorption 시킨다. 네 번째 step은 purge 시킨다. 결과적으로 self limited 한 식각이 이루어짐을 볼 수 있었다. 실제 공정을 MOS의 high-k dielectric에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU (North Carolina State University) CVC model로 구한 EOT (equivalent oxide thickness)는 변화가 없으면서 mos parameter인 Ion/Ioff ratio의 증가를 볼 수 있었다. 그 원인으로 XPS (X-ray photoelectron spectroscopy)로 gate oxide의 atomic percentage의 분석 결과 식각 중 발생하는 gate oxide의 edge에 trap의 감소로 기인함을 확인할 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.75.2-75.2
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• 2009

• Electrical & Electronic Materials
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• v.16 no.9
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• pp.62.3-63
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• 2003

• The Optical Journal
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• s.90
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• pp.60-65
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• 2004

현대의 정보통신 사회에 있어서 카메라는 여러 분야에 사용이 되고 있다. 카메라는 아날로그사진에서 피사체를 기록하기위한 필름을 사용하는데 이미지 센서는 빛을 변환하는 역할을 하는 필름대용품으로 사용되는 것이다. 이 이미지 센서는 전하결합소자(CCD : Charge Coupled Device)와 상보금속 산화물반도체(CMOS : Complementary Metal-Oxide-Semiconductor)가 대표적이다. 특히 디지털 카메라를 이용하여 과거의 카메

• Journal of the Semiconductor & Display Technology
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• v.13 no.3
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• pp.35-38
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• 2014

Flat panel displays fabricated on glass substrate use amorphous Si for data processing circuit. Recent progress in display technology requires a new material to replace the amorphous Si, and ZnO is a good candidate. ZnO is a wide bandgap (3.3 eV) semiconductor with high mobility and good optical transparency. ZnO is usually grown by sputtering using ZnO ceramic target. However, ceramic target is more expensive than metal target, and making large area target is very difficult. In this work we studied characteristics of ZnO thin-film transistor grown by rf sputtering using Zn metal target and $CO_2$. ZnO film was grown at $450^{\circ}C$ substrate temperature, with -70 V substrate bias voltage applied. By using these methods, our ZnO TFT showed $5.2cm^2/Vsec$ mobility, $3{\times}10^6$ on-off ratio, and -7 V threshold voltage.

• Electronics and Telecommunications Trends
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• v.38 no.6
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• pp.52-61
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• 2023

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.