• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.6
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• pp.2139-2151
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• 2014

Embedded system testing, especially long-term reliability testing, of flash memory solutions such as embedded multi-media card, secure digital card and solid-state drive involves strategic decision making related to test sample size to achieve high test coverage. The test sample size is the number of flash memory devices used in a test. Earlier, there were physical limitations on the testing period and the number of test devices that could be used. Hence, decisions regarding the sample size depended on the experience of human testers owing to the absence of well-defined standards. Moreover, a lack of understanding of the importance of the sample size resulted in field defects due to unexpected user scenarios. In worst cases, users finally detected these defects after several years. In this paper, we propose that a large number of potential field defects can be detected if an adequately large test sample size is used to target weak features during long-term reliability testing of flash memory solutions. In general, a larger test sample size yields better results. However, owing to the limited availability of physical resources, there is a limit on the test sample size that can be used. In this paper, we address this problem by proposing a self-adaptive reliability testing scheme to decide the sample size for effective long-term reliability testing.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.7
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• pp.70-79
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• 1996

To increase the functionality of the memories, previous studies have deifned faults models and proposed functional testing algorithms with low complexity. Although conventional testing depended strongly on functional (voltage) testing method, it couldn't detect short and open defects caused by gate oxide short and spot defect which can afect memory reliability. Therefore, IDDQ (quiescent power supply current) testing is required to detect defects and thus can obtain high reliability. In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in mOS FET and observe behavior of the memory by analyzing voltage at storge nodes of the memory and IDDQ resulting from PSPICE simulation. Finally, using this behavioral analysis, we propose a linear testing algorithm of complexity O(N) which can be applicable to both functional testing and IDDQ testing simultaneously to obtain high functionality and reliability.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.147-155
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• 2017

A new endurance test-pattern generation on NAND-flash memory is proposed to improve test cost. We mainly focus on the correlation between the data-pattern and the device error-rate during endurance testing. The novelty is the development of testing method using quasi-random pattern based on device architectures in order to increase the test efficiency during time-consuming endurance testing. It has been proven by the experiments using the commercial 32 nm NAND flash-memory. Using the proposed method, the error-rate increases up to 18.6% compared to that of the conventional method which uses pseudo-random pattern. Endurance testing time using the proposed quasi-random pattern is faster than that of using the conventional pseudo-random pattern since it is possible to reach the target error rate quickly using the proposed one. Accordingly, the proposed method provides more low-cost testing solutions compared to the previous pseudo-random testing patterns.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.72-85
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• 2007

The development of memory design and process technology enabled the production of high density memory. However, this increased the complexity of the memory making memory testing more complicated, and as a result, it brought about an increase in memory testing costs. Effective memory test algorithm must detect various types of defects within a short testing time, and especially in the case of port memory test algorithm, it must be able to detect single port memory defects, and all the defects in the dual port memory. The March A2PF algorithm proposed in this paper is an effective test algorithm that detects all types of defects relating to the duel port and single port memory through the short 18N test pattern.

• Journal of KIISE
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• v.43 no.9
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• pp.998-1007
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• 2016

In recent years, the cost of automotive ECU (Electronic Control Unit) has accounted for more than 30% of total car production cost. However, the complexity of testing and debugging an automotive ECU is increasing because automobile manufacturers outsource automotive ECU production. Therefore, a large amount of cost and time are spent to localize faults during testing an automotive ECU. In order to solve these problems, we propose a fault localization method in memory for developers who run the integration testing of automotive ECU. In this method, memory is partitioned by utilizing memory map, and fault-suspiciousness for each partition is calculated by utilizing memory update information. Then, the fault-suspicious region for partitions is decided based on calculated fault-suspiciousness. The preliminary result indicated that the proposed method reduced the fault-suspicious region to 15.01(%) of memory size.

• Journal of the Korea Computer Industry Society
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• v.6 no.2
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• pp.295-304
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• 2005

This paper presents the problem of exhaustive test generation for detection of coupling faults between cells in word-oriented memories. According to this fault model, contents of any w-bit memory word in a memory with n words, or ability tochange this contents, is influenced by the contents of any other s-1 words in the memory. A near optimal iterative method for construction of test patterns is proposed The systematic structure of the proposed test results in simple BIST implementations.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.5
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• pp.41-49
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• 2010

Being popularized the use of portable entertainment/information devices, the demand on flash memory has been also increased radically. In general, flash memory reveals various error patterns by the devices it is mounted, and thus the memory makers are trying to minimize error ratio in the final process through not only the electric test but also the data integrity test under the same condition as real application devices. This process is called an application-level memory test. Though currently various flash memory testing devices have been used in the production lines, most of the works related to memory test depend on the sensual abilities of human testers. In case of testing the flash memory for MP3 devices, the human testers are checking if the memory has some errors by hearing the audio played on the memory testing device. The memory testing process like this has become a bottleneck in the flash memory production line. In this paper, we propose an audio comparison technique to support the efficient flash memory test for MP3 devices. The technique proposed in this paper compares the variance change rate between the source binary file and the decoded analog signal and checks automatically if the memory errors are occurred or not.

• Korean Journal of Biological Psychiatry
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• v.4 no.2
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• pp.237-245
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• 1997

The study was designed to evaluate the significant roles of SSRI in rat of depression model. Chronic exposure to mild unpredictable stress has been found to depress the consumption of sweet 1% sucrose solutions in the Sprague-Dawley rats. We applied the variety of 11 types of stress regimens and identified depressive behaviours(developed by Willner) in 70 Sprague-Dawley rats. Rats in experiments were stratified into 6 groups, ie ; 3 kinds of SSRI(paroxetine, fluoxetine, sertraline), clomipramine, choline and saline control. Memory function was evaluated by passive avoidance learning and retention test. The authors determined how long memory retention would remain improved with 24 hour, 1 week, 2 weeks, 3 weeks, and 4 weeks at training-testing interval in depressive states of the Sprague-Dawley rats. The results were as follows ; 1) There were no significant differences between the 6 groups at the 24 hour training-testing interval. 2) The paroxetine treated group showed significant differences from the control group at the 1 week and 2 weeks training-testing interval. 3) The paroxetine and the fluoxetine treated groups showed singificant differences from the control group at 3 week training-testing interval. 4) The paroxetine and the choline treated groups showed significant differences from the control group at 4 week training-testing interval. In summary, paroxetine had an effect on long term memory processing from 1st week to 4th week. Also, fluoxetine(at 3rd week) and choline(at 4th week) had effect on long term memory processing. Sertraline, clomipramine were ineffective on memory processing during 4 weeks observation. Possible explanations why paroxetine had early effect on memory processing than the other selective serotonin reuptake inhibitors are rapid bioavailability, which is the characteristics of pharmacokinetics of paroxetine. In clinical situation, author carefully suggest that SSRI would be beneficial to improve the memory function caused by depressive neurochemical changes.

• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.67-71
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• 1999

In this paper, we design circuits embedded in memory chip which perform memory testing algorithms using BIST scheme to reduce testing time and cost for testing. In order to implement circuits for MSCAN, Marching and checkerboard test algorithms, which have widely used in memory testing, we survey structure of the BIST circuits and describe each block of BIST circuits by using VHDL. Thereafter, We verify behavior of each VHDL coding block and extract BIST circuits for target testing algorithms by CAD tool for simulation and synthesis. Extracted circuits have very low area overhead.