JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

Low Cost Endurance Test-pattern Generation for Multi-level Cell Flash Memory

  • Cha, Jaewon (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Cho, Keewon (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Yu, Seunggeon (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kang, Sungho (Department of Electrical and Electronic Engineering, Yonsei University)
  • Received : 2016.07.21
  • Accepted : 2016.10.19
  • Published : 2017.02.28
Download PDF
⟨ Previous Next ⟩

Abstract

A new endurance test-pattern generation on NAND-flash memory is proposed to improve test cost. We mainly focus on the correlation between the data-pattern and the device error-rate during endurance testing. The novelty is the development of testing method using quasi-random pattern based on device architectures in order to increase the test efficiency during time-consuming endurance testing. It has been proven by the experiments using the commercial 32 nm NAND flash-memory. Using the proposed method, the error-rate increases up to 18.6% compared to that of the conventional method which uses pseudo-random pattern. Endurance testing time using the proposed quasi-random pattern is faster than that of using the conventional pseudo-random pattern since it is possible to reach the target error rate quickly using the proposed one. Accordingly, the proposed method provides more low-cost testing solutions compared to the previous pseudo-random testing patterns.

Keywords

References

  1. Kim, Eun-Kyeom, et al. "Nonvolatile memory characteristics of double-stacked Si nanocluster floating gate transistor." JSTS: Journal of Semiconductor Technology and Science, 2008.
  2. Hogan, Damien, Tom Arbuckle, and Conor Ryan. "Estimating MLC NAND flash endurance: a genetic programming based symbolic regression application." Proceedings of the 15th annual conference on Genetic and evolutionary computation. ACM, 2013.
  3. Huang, Min, et al. "An endurance-aware metadata allocation strategy for MLC NAND flash memory storage systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35.4 (2016): 691-694. https://doi.org/10.1109/TCAD.2015.2474394
  4. Cha, Jaewon, et al. IEEE Transactions on Semiconductor Manufacturing, pp.399-407, vol.28, no. 3, 2015. https://doi.org/10.1109/TSM.2015.2429211
  5. "Jedec standard JESD22a117b Electrically Erasable Programmable ROM(EEPROM) Program/Erase Endurance and Data Retention Stress Test," 2009, www.jecec.org.
  6. Park, Ki-Tae, et al. "Three-dimensional 128 Gb MLC vertical NAND flash memory with 24-WL stacked layers and 50 MB/s high-speed programming." Solid-State Circuits, IEEE Journal of 50.1 (2015): 204-213. https://doi.org/10.1109/JSSC.2014.2352293
  7. Tanaka, Tomoharu, et al. "7.7 A 768Gb 3b/cell 3Dfloating-gate NAND flash memory." 2016 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2016.
  8. Yang, Jeff. "High-efficiency SSD for reliable data storage systems." Proc. Flash Memory Summit (2011).
  9. Yu, Tingting, et al. "A new decompressor with ordered parallel scan design for reduction of test data and test time." Circuits and Systems (ISCAS), 2015 IEEE International Symposium on. IEEE, 2015.
  10. Min, Fan, Qinghua Hu, and William Zhu. "Feature selection with test cost constraint." International Journal of Approximate Reasoning 55.1 (2014): 167-179 https://doi.org/10.1016/j.ijar.2013.04.003
  11. S. Tanakamaru et al., "Highly reliable and low power SSD using asymmetric coding and stripe bitline-pattern elimination programming," IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 85-96, Jan. 2012. https://doi.org/10.1109/JSSC.2011.2170637
  12. Y. Cai et al., "Data retention in MLC NAND flash memory: Characterization, optimization, and recovery," IEEE Int. Symp. High Performance Comput. Archit. (HPCA), Burlingame, CA, USA, Feb. 2015, pp. 551-563.
  13. J. Moon et al., "Statistical characterization of noise and interference in NAND flash memory," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 8, pp. 2153-2164, Aug. 2013. https://doi.org/10.1109/TCSI.2013.2239116
  14. Moriyasu, Takanori, and Satoshi Ohtake. "A method of one-pass seed generation for LFSRbased deterministic/pseudo-random testing of static faults." 2015 16th Latin-American Test Symposium (LATS). IEEE, 2015.
  15. Cai, Yu, et al. "Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis." 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2012.
  16. J. Cha and S. Kang, "Data Randomization Scheme for Endurance Enhancement and Interference Mitigation of Multilevel Flash Memory Devices " ETRI Journal, vol. 35, no. 1, Feb. 2013, pp. 166-169. https://doi.org/10.4218/etrij.13.0212.0273
  17. Park, Ki-Tae, et al. "A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories." Solid-State Circuits, IEEE Journal of 43.4 (2008): 919-928. https://doi.org/10.1109/JSSC.2008.917558
  18. Cai, Yu, et al. "Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation." Computer Design (ICCD), 2013 IEEE 31st International Conference on. IEEE, 2013.
  19. Aritome, Seiichi. "NAND Flash Memory Revolution." 2016 IEEE 8th International Memory Workshop (IMW). IEEE, 2016.
  20. Park, Sung-Kye. "Technology Scaling Challenge and Future Prospects of DRAM and NAND Flash Memory." 2015 IEEE International Memory Workshop (IMW). IEEE, 2015.
  21. "1H2016_Product_Catalog," www.skhynix.com.