• International Journal of Internet, Broadcasting and Communication
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• v.11 no.1
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• pp.69-74
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• 2019

The compiler is the key of the prototyping framework for the new memory system. These compiler-centric prototyping tools have several components, including compiler, linker, assembler, and standard libraries. It takes a lot of cost and man power to develop it all at zero base. Therefore, developer usually use a development framework to develop these prototyping tools efficiently. These development frameworks should be free of licensing issues when considering the commercialization of development results. Thus, developer should investigate the development framework, which is free from licensing issues and that provides all of the development environment to enable actual execution. There are three representative compiler-centric development frameworks: GCC, Clang (LLVM), and MS visual studio. There are some differences depending on the release version among them. And, there are some limitations to the freeware and commercial use. We chose LLVM here to explain the development of prototyping tools. This information will help accelerate the development of prototyping tools and will help reduce system development costs.

• Korean Journal of Biological Psychiatry
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• v.16 no.4
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• pp.238-245
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• 2009

Objectives : Mild Alzheimer's disease(AD) is uncertain to be related to visuospatial working memory subsystem dysfunction. We used the self ordered pointing test(SOPT) to find the characteristics of visuospatial working memory in mild AD. Methods : We compared the visuospatial working memory abilities of 20 patients with mild AD and 20 normal elderly controls(NC) using SOPT, of which stimuli consisted of two stimuli types(A : abstract, C : concrete) and two stimuli numbers(8 and 12). Therefore, working memory was tested using C8, C12, A8, and A12 stimuli conditions in SOPT. Mixed-model ANOVA was conducted with the AD and NC groups as between-subjects factor, with stimuli types and stimuli numbers as the within-subjects factors and with SOPT error rates as the dependent variable. Results : The AD group showed higher error rates in SOPT than the NC group. The NC group showed low error rates in concrete stimuli than in abstract stimuli and in small stimuli numbers than in large stimuli numbers. And the AD group showed no differences between stimuli types or stimuli numbers. Conclusion : AD patients showed a poor performance in visuospatial working memory using concrete stimuli. The result suggests that there is a non-transformation from visual input to phonological working memory in AD. Patients with AD showed a poor performance although in small stimuli number condition of SOPT. It suggests that in AD, visuospatial working memory is not working well although in low central executive loads.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06a
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• pp.337-338
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• 2008

• Journal of KIISE:Databases
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• v.32 no.1
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• pp.12-23
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• 2005

In the past decade, advances in speed of commodity CPUs have iu out-paced advances in memory latency Main-memory access is therefore increasingly a performance bottleneck for many computer applications, including database systems. To reduce memory access latency, cache memory incorporated in the memory subsystem. but cache memories can reduce the memory latency only when the requested data is found in the cache. This mainly depends on the memory access pattern of the application. At this point, previous research has shown that B+ trees perform much faster than T-trees because B+ trees are more cache conscious than T-trees, and also proposed 'Cache Sensitive B+trees' (CSB. trees) that are more cache conscious than B+trees. The goal of this paper is to make T-trees be cache conscious as CSB-trees. We propose a new index structure called a 'Cache Sensitive T-trees (CST-trees)'. We implemented CST-trees and compared performance of CST-trees with performance of other index structures.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2001.04a
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• pp.61-68
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• 2001

A parallel nonlinear analysis program of prestressed concrete frame is migrated on a PC cluster system and a massively parallel processing system, CRAY T3E system, using MPI. The PC cluster system is configured with Pentium Ⅲ class PCs and fast ethernet. The CRAY T3E system is composed of a set of nodes each containing one Processing Element (PE), a memory subsystem and its distributed memory interconnect network. Parallel computing algorithms are implemented on element-wise processing parts including the calculation of stiffness matrix, element stresses and determination of material states, check of material failure and calculation of unbalanced loads. Parallel performance of the migrated program is evaluated through typical numerical examples.

• Journal of the Korea Society for Simulation
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• v.1 no.1
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• pp.87-102
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• 1992

This paper presents the development of event-driven system level simulation tool SMPLE(Smpl Extende, an extention fo smpl) and its application to the performance analysis of multiprocessor computer systems. Because of its data structure, it is very difficult to change, expand or add new functions to simulation language smpl implemented by MacDougall. In SMPLE, we change data structure with structure and pointer, add new functions, and enable dynamic memory management. Using new data structure, facilities, and functions added in SMPLE, we simulate job processing of a shared bus multiprocessor system with autonomous hierarchical I/O subsystem. We set system performance contribution of subsystems and units. The impact of disk I/O on system performance is evaluated under vairous conditions of number of processors, processing power, memory access time and disk seek time.

• The Journal of the Korea Contents Association
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• v.15 no.4
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• pp.9-16
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• 2015

On modern operating systems such as Linux, virtual memory is a general way to provide a large address space to applications by using main memory and storage devices. Recently, storage devices have been improved in terms of latency and bandwidth, and it is expected that applications with large memory show high-performance if next-generation storage devices are considered. However, due to the overhead of virtual memory subsystem, the paging system can not exploit the performance of next-generation storage devices. In this study, we propose several optimization techniques to extend memory with next-generation storage devices. The techniques are to allocate block addresses of storage devices for write-back operations as well as to configure the system parameters, and we implement the techniques on Linux 3.14.3. Our evaluation through using multiple benchmarks shows that our system has 3 times (/24%) better performance on average than the baseline system in the micro(/macro)-benchmark.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.5
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• pp.537-541
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• 2008

Log-Structured File System(LFS) is a disk based file system that is optimized for improving the write performance. LFS gathers dirty data in memory as long as possible, and flushes all dirty data sequentially at once. In a real system, however, maintaining dirty data in memory should be flushed into a disk to meet file system consistency issues even if more memory is still available. This synchronizations increase the cleaner overhead of LFS and make LFS to write down more metadata into a disk. In this paper, by adapting Non-volatile RAM(NV-RAM) we modifies LFS and virtual memory subsystem to guarantee that LFS could gather enough dirty data in the memory and reduce small disk writes. By doing so, we improves the performance of LFS by around 2.5 times than the original LFS.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.10 no.1
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• pp.95-105
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• 2006

The speed of hard disk which is based on mechanical operation is more slow than processor. The growth of processor speed is rapid by semiconductor technology, but the growth of disk speed which is based on mechanical operation is not enough. Buffer cache in main memory and disk cache in disk controller have been used in computer system to solve the speed gap between processor and I/O subsystem. In this paper, an efficient buffer cache and disk cache management scheme was proposed to restrict duplicated disk block between buffer cache and disk cache. The performance of the proposed algorithm was evaluated by simulation.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.4
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• pp.9-18
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• 2013

Flash memory is mostly used on smart devices and embedded systems because of its nonvolatile memory, low power, quick I/O, resistant shock, and other benefits. Generally the typical file systems base on the NAND flash memory are YAFFS2, JFFS2, UBIFS, and etc. In this paper, we had variously made an experiment regarding I/O performance using our schemes and the UBIFS of the latest Linux Kernel. The proposed I/O performance analyses were classified as a sequential access and a random access. Our experiment consists of 6 cases using kmalloc(), vmalloc(), and kmem_cache(). As a result of our experiment analyses, the sequential reading and the sequential rewriting increased by 12%, 11% when the Case 2 has applied vmalloc() and kmalloc() to the UBI subsystem and the UBIFS. Also, the performance improved more by 7.82%, 6.90% than the Case 1 at the random read and the random write.