• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.183-186
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• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.

• Journal of information and communication convergence engineering
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• v.21 no.2
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• pp.117-129
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• 2023

High-utility itemset mining (HIUM) has emerged as a key data-mining paradigm for object-of-interest identification and recommendation systems that serve as frequent itemset identification tools, product or service recommendation systems, etc. Recently, it has gained widespread attention owing to its increasing role in business intelligence, top-N recommendation, and other enterprise solutions. Despite the increasing significance and the inability to provide swift and more accurate predictions, most at-hand solutions, including frequent itemset mining, HUIM, and high average- and fast high-utility itemset mining, are limited to coping with real-time enterprise demands. Moreover, complex computations and high memory exhaustion limit their scalability as enterprise solutions. To address these limitations, this study proposes a model to extract high-utility frequent closed itemsets based on an improved cumulative summary list structure (CSLFC-HUIM) to reduce an optimal set of candidate items in the search space. Moreover, it employs the lift score as the minimum threshold, called the cumulative utility threshold, to prune the search space optimal set of itemsets in a nested-list structure that improves computational time, costs, and memory exhaustion. Simulations over different datasets revealed that the proposed CSLFC-HUIM model outperforms other existing methods, such as closed- and frequent closed-HUIM variants, in terms of execution time and memory consumption, making it suitable for different mined items and allied intelligence of business goals.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.368.1-368.1
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• 2014

We proposed amorphous GeSe-based ReRAM device of metal-insulator-metal (M-I-M) structure. The operation characteristics of memory device occured unipolar switching characteristics. By introducing the concepts of valance-alternation-pairs (VAPs) and chalcogen vacancies, the unipolar resistive switching operation had been explained. In addition, the current transport behavior were analyzed with space charge effect of VAPs, Schottky emission in metal/GeSe interface and P-F emission by GeSe bulk trap in mind. The GeSe ReRAM device of M-I-M structure indicated the stable memory switching characteristics. Furthermore, excellent stability, endurance and retention characteristics were also verified.

• International Journal of Aeronautical and Space Sciences
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• v.7 no.1
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• pp.91-98
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• 2006

The thermomechanical behaviors of SMA thin film actuator and their application are investigated. The numerical algorithm of the 2-D SMA thermomechanical constitutive equation is developed and implemented into the ABAQUS finite element program by using the user defined material (UMAT) subroutine. To verify the numerical algorithm of SMAs, the results are compared with experimental data. For the application of SMA thin film actuator, the methodology to maintain the precise configuration of inflatable membrane structure is demonstrated.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.483-484
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• 2006

In this paper, we fabricated the organic bi-stable devices under the different condition from the other groups and analyzed the electrical characteristics. Then we investigated the effects of the device structure such as organic layer thickness, middle metal layer thickness and middle metal layer deposition rate on the memory characteristics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.169-174
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• 2014

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.901-909
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• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.80-81
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• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a sample of PRAM with thermal protected layer. We have investigated the phase transition behaviors in function of process factor including thermal protect layer. As a result, we have observed that set voltage and duration of protect layer are more improved than no protect layer.

• International Journal of Internet, Broadcasting and Communication
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• v.13 no.3
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• pp.104-108
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• 2021

In order to improve performance in IoT, edge computing system, a memory is usually configured in a hierarchical structure. Based on the distance from CPU, the access speed slows down in the order of registers, cache memory, main memory, and storage. Similar to the change in performance, energy consumption also increases as the distance from the CPU increases. Therefore, it is important to develop a technique that places frequently used data to the upper memory as much as possible to improve performance and energy consumption. However, the technique should solve the problem of cache performance degradation caused by lack of spatial locality that occurs when the data access stride is large. This study proposes a technique to selectively place data with large data access stride to a software-controlled cache. By using the proposed technique, data spatial locality can be improved by reducing the data access interval, and consequently, the cache performance can be improved.

• Proceedings of the Korean Society For Composite Materials Conference
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• 2005.04a
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• pp.226-230
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• 2005

This paper presents the actuation performance of a conducting shape memory polyurethane (CSMPU) actuator. We introduced a concept of shape memory polyurethane activated by electric power while conventional shape memory polyurethanes are activated by external heat source. A conducting shape memory polyurethane actuator was manufactured by adding cabon nano-tube to conventional shape memory polyurethane. The main problem of the previous CSMPU was bad dispersion of carbon nano-tubes in polyurethane. In this paper, we have tried to find manufacturing method to solve the dispersion problem. With a lot of elaborative works, we have developed conducting shape memory polyurethane actuator with good electrical performance. The actuation performance of the developed conducting shape memory polyurethane actuator was measured and assessed.