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A Technique for Improving the Performance of Cache Memories

  • Cho, Doosan (Department of Electrical & Electronic Engineering, Sunchon National Univ.)
  • Received : 2021.06.25
  • Accepted : 2021.07.03
  • Published : 2021.08.31

Abstract

In order to improve performance in IoT, edge computing system, a memory is usually configured in a hierarchical structure. Based on the distance from CPU, the access speed slows down in the order of registers, cache memory, main memory, and storage. Similar to the change in performance, energy consumption also increases as the distance from the CPU increases. Therefore, it is important to develop a technique that places frequently used data to the upper memory as much as possible to improve performance and energy consumption. However, the technique should solve the problem of cache performance degradation caused by lack of spatial locality that occurs when the data access stride is large. This study proposes a technique to selectively place data with large data access stride to a software-controlled cache. By using the proposed technique, data spatial locality can be improved by reducing the data access interval, and consequently, the cache performance can be improved.

Keywords

Acknowledgement

This work was supported by a research promotion program of SCNU.

References

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