• 한국통신학회논문지
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• 제37A권10호
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• pp.827-833
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• 2012

고전력 증폭기의 비선형 특성은 통신 시스템의 성능을 저하시키는 주요한 요인이다. 일반적인 전치왜곡기는 고전력 증폭기의 비선형 문제를 효과적으로 보상가능 하다. 그러나 고속 데이터 전송 시에 발생되는 메모리 효과는 보상하지 못하는 문제점이 있다. 메모리 효과를 효과적으로 보상하기 위해서 송신 단에서 다양한 적응형 전치왜곡기 방식이 제안되었다. 위성 통신 시스템에서는 기존의 적응형 전치왜곡기를 사용하기 위해서는 위성에 적응형 회로를 설계해야 되는 부담이 있다. 본 논문에서는 메모리 효과를 가진 고전력 증폭기의 비선형 문제를 보상하기 위해서 수신기 포함 폐루프 전치왜곡기를 제안한다. 제안한 시스템은 위성에서 전치왜곡기를 사용하지 않고 지상국에서만 전치왜곡기를 사용함으로써 위성의 복잡도와 설계비용을 낮출 수 있을 것으로 예상된다.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.118-123
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• 2020

In this paper, the design method of asynchronous nonvolatile memory module that can efficiently process and store large amounts of data without loss when the power turned off is proposed and implemented. PSRAM, which takes advantage of DRAM and SRAM, was used for data processing, and NAND flash memory was used for data storage and backup. The problem of a lot of signal interference due to the characteristics of memory devices was solved through PCB design using high-density integration technology. In addition, a boost circuit using the super capacitor of 0.47F was designed to supply sufficient power to the system during the time to back up data when the power is off. As a result, an asynchronous nonvolatile memory module was designed and implemented that guarantees reliability and stability and can semi-permanently store data for about 10 years. The proposed method solved the problem of frequent data loss in industrial sites and presented the possibility of commercialization by providing convenience to users and managers.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1989년도 한국자동제어학술회의논문집; Seoul, Korea; 27-28 Oct. 1989
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• pp.372-376
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• 1989

One of the major difficulties with modular approach model of separation process simulation is initial guess problem. Only accurate initial guess make the problem converge and large computer memory and calculating time are required. In this study, we use the initial bottom guess value same as given feed condition and update the value the .theta.method. So we examine;(1)the problem converges using initial guess with large range, (2)computer memory and calculating time are reduced considerably.

• 생물정신의학
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• 제4권1호
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• pp.3-11
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• 1997

Disturbances in memory are the most common problem in patients with an organic mental syndrome. Other patients with significant psychiatric disorders also often have difficulty with memory. So it is very important in the clinical practice of psychiatry to understand the biological and neurocognitive mechanisms of memory proessing, and to develop the assessment tools with which memory function can be evaluated reliably and validly. Moreover, memory researches provide an important viewpoint from which we can understand the pathophysiological mechanisms of major neuropsychiatric illnesses. This article focuses on our understanding of memory functions in clinical and neurobiological aspects. The relevant material will be presented in four parts : 1) terminologies needed in defining major stages of various types of memory processing : 2) neurochemical and neuroanatomical basis of memory processing : 3) brief bed-side screening tests and more comprehensive neuropsychological tests for the evaluation of memory function : 4) the characteristics of memory dysfunction in several major psychiatric illnesses.

• 대한임베디드공학회논문지
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• 제13권3호
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• pp.125-131
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• 2018

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

• 한국컴퓨터정보학회논문지
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• 제21권5호
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• pp.1-10
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• 2016

Magnetic disks have been used for decades in auxiliary storage devices of computer systems. In recent years, the use of NAND flash memory, which is called SSD, is increased as auxiliary storage devices. However, NAND flash memory, unlike traditional magnetic disks, necessarily performs the erase operation before the write operation in order to overwrite data and this leads to degrade the system lifetime and performance of overall NAND flash memory system. Moreover, NAND flash memory has the lower endurance, compared to traditional magnetic disks. To overcome this problem, this paper proposes EPET (Enhanced Prediction and Elapsed Time) wear leveling technique, which is especially efficient to portable devices. EPET wear leveling uses the advantage of PET (Prediction of Elapsed Time) wear leveling and solves long-term system failure time problem. Moreover, EPET wear leveling further improves space efficiency. In our experiments, EPET wear leveling prolonged the first bad time up to 328.9% and prolonged the system lifetime up to 305.9%, compared to other techniques.

• International journal of advanced smart convergence
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• 제6권1호
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• pp.26-31
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• 2017

When mobile navigator device accesses data randomly, the cache memory performance is rapidly deteriorated due to low memory access locality. For instance, GPS (General Positioning System) of navigator program for automobiles or drones, that are currently in common use, uses data from 32 satellites and computes current position of a receiver. This computation of positioning is the major part of GPS which accounts more than 50% computation in the program. In this computation task, the satellite signals are received in real time and stored in buffer memories. At this task, since necessary data cannot be sequentially stored, the data is read and used at random. This data accessing patterns are generated randomly, thus, memory system performance is worse by low data locality. As a result, it is difficult to process data in real time due to low data localization. Improving the low memory access locality inherited on the algorithms of conventional communication applications requires a certain optimization technique to solve this problem. In this study, we try to do optimizations with data and memory to improve the locality problem. In experiment, we show that our case study can improve processing speed of core computation and improve our overall system performance by 14%.

• Steel and Composite Structures
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• 제38권4호
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• pp.447-462
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• 2021

In this work, we consider a problem in the context of thermoelectric materials with memory-dependent derivative for a half space which is assumed to have variable thermal conductivity depending on the temperature. The Lamé's modulii of the half space material is taken as a function of the vertical distance from the surface of the medium. The surface is traction free and subjected to a time dependent thermal shock. The problem was solved by using the Laplace transform method together with the perturbation technique. The obtained results are discussed and compared with the solution when Lamé's modulii are constants. Numerical results are computed and represented graphically for the temperature, displacement and stress distributions. Affectability investigation is performed to explore the thermal impacts of a kernel function and a time-delay parameter that are characteristic of memory dependent derivative heat transfer in the behavior of tissue temperature. The correlations are made with the results obtained in the case of the absence of memory-dependent derivative parameters.

• 반도체디스플레이기술학회지
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• 제21권3호
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• pp.1-6
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• 2022

Modern computer systems usually have special hardware for operations used in deep learning workload even edge computing environment. Non-volatile memories (NVMs) have been considered for alternative memory storage because they consume little static energy and occupy small area. However, there is a problem for NVMs to be directly adopted. An NVM cell has limited write endurance, so that the lifetime of NVM-based memory system is much shorter than that of conventional memory system. To overcome this problem for the deep learning system, this paper proposes a novel method to extend the lifetime based on the analysis of the deep learning workloads. If an incoming block has more than a predefined number of frequently used values, the cacheline is defined as write friendly block. During the victim selection, the cacheline has lower possibility to be chosen as victim. The experimental results show that the lifetime is increased by about 50% and energy consumption is decreased by 3% with a little performance hurt.