Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
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Design of Asynchronous Non-Volatile Memory Module Using NAND Flash Memory and PSRAM

낸드 플래시 메모리와 PSRAM을 이용한 비동기용 불휘발성 메모리 모듈 설계

  • Kim, Tae Hyun (Semiconductor Engineering of Cheongju University) ;
  • Yang, Oh (Semiconductor Engineering of Cheongju University) ;
  • Yeon, Jun Sang (WOOJIN Industrial System Co. Ltd.)
  • 김태현 (청주대학교 반도체공학과) ;
  • 양오 (청주대학교 반도체공학과) ;
  • 연준상 (우진산전(주))
  • Received : 2020.09.17
  • Accepted : 2020.09.23
  • Published : 2020.09.30
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Abstract

In this paper, the design method of asynchronous nonvolatile memory module that can efficiently process and store large amounts of data without loss when the power turned off is proposed and implemented. PSRAM, which takes advantage of DRAM and SRAM, was used for data processing, and NAND flash memory was used for data storage and backup. The problem of a lot of signal interference due to the characteristics of memory devices was solved through PCB design using high-density integration technology. In addition, a boost circuit using the super capacitor of 0.47F was designed to supply sufficient power to the system during the time to back up data when the power is off. As a result, an asynchronous nonvolatile memory module was designed and implemented that guarantees reliability and stability and can semi-permanently store data for about 10 years. The proposed method solved the problem of frequent data loss in industrial sites and presented the possibility of commercialization by providing convenience to users and managers.

Keywords

References

  1. Tae Hyun Kim, Oh Yang, "Design and Implementation of Multi-monitoring System for Motor Pump", Journal of the Semiconductor & Display Technology, Vol.18, No.4, pp.81-86, 2019.12.
  2. Seok Man Kim, Min Seok Oh, Kyoung Rok Cho, "Efficient Policy ECC Parity Storing of NAND Flash Memory", The Journal of the Korea Contents Association, Vol.16, No.10, pp.477-482, 2016.09. https://doi.org/10.5392/JKCA.2016.16.10.477
  3. Dong Hyuk Park, Jae Jin Lee, Gi Ju Yang, "Modulation Code for Removing Error Patterns on 4-Level NAND Flash Memory", The Journal of Korea Information and Communications Society, Vol.35, No.12, pp.965-970, 2010.12.
  4. Po Yuan Chen, Chin Lung Su, Chao Hsun Chen, Cheng Wen Wu, "Generalization of an Enhanced ECC Methodology for Low Power PSRAM", IEEE TRANSACTIONS ON COMPUTERS, Vol.62, No.7 pp.1318-1331, 2013.7. https://doi.org/10.1109/TC.2012.98
  5. Won Taek Lee, Jin Woo Jang, Joon Il Kim, Soon Shin Choi, Yong Jee, "Analysis of Characteristic Impedance for FBGA Memory Module Package", Proceedings of autumn Symposium The Institute of Electronics Engineers, Vol.29, No.2, pp.482-485, 2006.
  6. Hyun Wook Park, Sang Won Shim, Yeon Bae Chung, "A current sense amplifier for low-voltage and highspeed SRAM", Proceedings of autumn Symposium The Institute of Electronics Engineers, Vol.28, No.2, pp.727-730, 2005.
  7. Jun Sang Yeon, Oh Yang "Implementation of Communication to Flexibly Configure the Number of Railway Cars", Journal of the Semiconductor & Display Technology, Vol.15, No.4, pp.61-66, 2016.12.
  8. Heon Guk Lee, Oh Yang, "Implementtation of Monitoring and Control System for Fire Engine Pump using the AJAX", Journal of the Semiconductor & Display Technology, Vol.15, No.3, pp.40-45, 2016.09.
  9. CYPRESS, "CY14B116L - ZS25XI Datasheet 16-Mbit (2048K $\times$ 8/1024K $\times$ 16/512K $\times$ 32) nvSRAM", pp.01-39, 2019.
  10. Jung Won Kim, Seung Kyun Kim, Jae Jin Lee, Chang Hee Jung, Duk Kyun Woo, "Memory Hierarchy Optimization in Embedded Systems using On-Chip SRAM", Journal of the Korea Information Science Society (a) : computer systems and theory, Vol.36, No.2, pp.102-110, 2009.4.
  11. In Sung Gook, Jae Min Lee, "A Parallel Structure of SRAMs in embedded DRAMs for Testability", Journal of Korea institute of information, electronics, and communication technology, Vol.3, No.3, pp.3-7, 2010.
  12. Integrated Silicon Solution Inc, "IS66WV51216EBL - 70BLI Datasheet 64Mb Async/Page PSRAM", pp.01-34, 2018.8.
  13. Ji Eun Oh, Seok Ju Han, "Performance Comparison of Multi-level Coding Schemes for NAND Flash Memory", IEIE Transactions on Smart Processing and Computing, Vol.7, No.6, pp.496-504, 2018.12. https://doi.org/10.5573/ieiespc.2018.7.6.496