• Journal of IKEEE
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• v.27 no.4
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• pp.644-649
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• 2023

As the cell spacing decreases during the scaling process of DRAM(Dynamic Random Access Memory), the reduction in STI(Shallow Trench Isolation) thickness leads to an increase in sub-threshold leakage due to the passing word line effect. The increase in sub-threshold leakage current caused by the voltage applied to adjacent passing word lines affects the data retention time and increases the number of refresh operations, thereby contributing to higher power consumption in DRAM. In this paper, we identify the causes of the passing word line effect through TCAD Simulation. As a result, we confirm the DRAM operational conditions under which the passing word line effect occurs, and observe that this effect alters the proportion of the total leakage current attributable to different causes. Through this, we recognize the necessity to consider not only leakage currents due to GIDL(Gate Induced Drain Leakage) but also sub-threshold leakage currents, providing guidance for improving DRAM structure.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.57-64
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• 2007

This paper proposed the low power texture cache for mobile 3D graphics accelerators. It is very important to reduce the leakage power in the standby mode for mobile 3D graphics accelerators and the memory access latency of texture mapping in the active mode which needs a large memory bandwidth. The proposed structure reduces the leakage power using variable threshold values of power mode transitions according to the selected texture filtering algorithms of application programs, which has the run time gain for texture mapping. In the trace driven cache simulation the proposed structure shows the best 7% performance gain to the previous MSA cache according to the new performance metric considering both normalized leakage power and run time impact.

• The Korean Journal of Ceramics
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• v.2 no.2
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• pp.95-101
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• 1996

Variations of the leakage current behaviors and interface potential barrier $({\Phi}_B)$ of rf-sputter deposited (Ba, Sr)$TiO_3$ (BST) thin films with thicknesses ranging from 20 nm to 150nm are investigated as a function of the thickness and bias voltages. The top and bottom electrodes are dc-sputter-deposited Pt films. ${\Phi}_B$ critically depends on the BST film deposition temperature, postannealing atmosphere and time after the annealing. The postannealing under $N_2$ atmosphere results in a high interface potential barrier height and low leakage current. Maintaining the BST capacitor in air for a long time reduces the ${\Phi}_B$ from about 2.4 eV to 1.6 eV due to the oxidation. ${\Phi}_B$ is not so dependent on the film thickness in this experimental range. The leakage conduction mechanism is very dependent on the BST film thickness; the 20 nm thick film shows tunneling current, 30 and 40 nm thick films show Shottky emission current.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.329-329
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• 2012

Mobile 기기로 둘러싸여있는 현대의 환경에서 Flash memory에 대한 중요성은 날로 더해가고 있다. Flash memory의 가격 경쟁력 강화와 사용되는 기기의 소형화를 위해 flash memory의 비례축소가 중요한 문제로 부각되고 있다. 그러나 다결정 실리콘을 플로팅 게이트로 이용하는planar flash memory 소자의 경우 비례 축소 시 short channel effect 와 leakage current, subthreshold swing의 증가로 인한 성능저하와 같은 문제들로 인해 한계에 다다르고 있다. 이를 해결하기 위해 CTF 메모리 소자, nanowire FET, FinFET과 같은 새로운 구조를 가지는 메모리소자에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 22 nm 게이트 크기의 FinFET 구조를 가지는 플래시 메모리소자에서 fin의 두께와 높이의 변화에 따른 메모리 소자의 전기적 특성을 3-dimensional 구조에서 technology computer aided design ( TCAD ) tool을 이용하여 시뮬레이션 하였다. 본 연구에서는 3D FinFET 구조를 가진 플래시 메모리에 대한 시뮬레이션 하였다. FinFET 구조에서 채널영역은 planar 구조와 다르게 표면층이 multi-orientation을 가지므로 본 계산에서는 multi-orientation Lombardi mobility model을 이용하여 계산하였다. 계산에 사용된 FinFET flash memory 구조는 substrate의 도핑농도는 $1{\times}10^{18}$로 하였으며 source, drain, gate의 도핑농도는 $1{\times}10^{20}$으로 설정하여 계산하였다. Fin 높이는 28 nm로 고정한 상태에서 fin의 두께는 12 nm부터 28nm까지 6단계로 나누어서 각 구조에 대한 프로그램 특성과 전기적 특성을 관찰 하였다. 계산결과 FinFET 구조의 fin 두께가 두꺼워 질수록 채널형성이 늦어져 threshold voltage 값이 커지게 되고 subthreshold swing 값 또한 증가하여 전기적 특성이 나빠짐을 확인하였다. 각 구조에서의 전기장과 전기적 위치에너지의 분포가 fin의 두께에 따라 달라지므로써 이로 인해 프로그램 특성과 전기적 특성이 변화함을 확인하였다.

• Journal of electromagnetic engineering and science
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• v.9 no.3
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• pp.152-158
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• 2009

We have developed a novel digital feedback predistortion(DFBPD) linearization based on RF feedback PD for the wide bandwidth modulated signals. The wideband PD operation is carried out by combining the DFBPD and memory lookup table(LUT). To experimentally demonstrate the linearization performance of the proposed PD technique for wideband signal, a class-AB amplifier using an LDMOSFET MRF6S23140 with 140-W peak envelope power is employed at 2.345 GHz. For a forward-link 2FA wideband code-division multiple-access signal with 10 MHz carrier spacing, the proposed DFBPD with memory LUT delivers the adjacent channel leakage ratio at an 10 MHz offset of -56.8 dBc, while those of the amplifier with and without DFBPD are -43.2 dBc and -41.9 dBc, respectively, at an average output power of 40 dBm. The experimental result shows that the new DFBPD with memory LUT provides a good linearization performance for the signal with wide bandwidth.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.87-95
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• 2016

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.439-444
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• 2005

We investigated the structural and electrical properties of BLT films grown on Si covered with $ZrO_{2}$ buffer layer. The BLT thin film and $ZrO_{2}$ buffer layer were fabricated using a metalorganic decomposition method. The electrical properties of the MFIS structure were investigated by varying thickness of the $ZrO_{2}$ layer. AES and TEM show no interdiffusion and reaction that suppressed using the $ZrO_{2}$ film as a buffer layer The width of the memory window in the C-V curves for the MFIS structure decreased with increasing thickness of the $ZrO_{2}$ layer. It is considered that the memory window width of MFIS is not affected by remanent polarization. Leakage current density decreased by about four orders of magnitude after using $ZrO_{2}$ buffer layer. The results show that the $ZrO_{2}$ buffer layers are prospective candidates for applications in MFIS-FET memory devices.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.4
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• pp.180-186
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• 2002

This paper describes on the development of power detection system with one-chip microcontroller. The designed system is composed of power detection circuits and analyzing software. The system detects, 3-phases voltage, 3-phases current, external temperature, leakage current and stores in flash memory. AT89C52 was used as CPU and AM29F040B was used as memory to store the data. The analysis saftware was developed to detect the cause of the electrical fire incidents. With a data-compression technology, the data can be stored for the 43.5 days in a normal state, four hours and fifteen minutes in emergency state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.358-358
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• 2010

To improve the programming/erasing speed and leakage current of multiple dielectric stack tunnel barrier engineering (TBE) Non-volatile memory, We propose a new concept called staggered structure of TBE memory. In this study, We fabricated staggered structure capacitor on $Si_3N_4$ stacked HfAlO and measured C-V curve that can observe tunneling characteristic of this device as various annealing temperature compared with that of single layer $SiO_2$ capacitor.

• ETRI Journal
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• v.32 no.3
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• pp.406-413
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• 2010

In order to guarantee the proper operation of a recessed channel array transistor (RCAT) pseudo SRAM, the back-bias voltage must be changed in response to changes in temperature. Due to cell drivability and leakage current, the obtainable back-bias range also changes with temperature. This paper presents a pseudo SRAM for mobile applications with an adaptive back-bias voltage generator with a negative temperature dependency (NTD) using an NTD VBB detector. The proposed scheme is implemented using the Samsung 100 nm RCAT pseudo SRAM process technology. Experimental results show that the proposed VBB generator has a negative temperature dependency of -0.85 $mV/^{\circ}C$, and its static current consumption is found to be only 0.83 ${\mu}A$@2.0 V.