Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
권호 표지
DOI QR코드

DOI QR Code

Analysis of Passing Word Line Induced Leakage of BCAT Structure in DRAM

BCAT구조 DRAM의 패싱 워드 라인 유도 누설전류 분석

  • Su Yeon, Kim (Dept, of ICT Convergence System Engineering and Electronic Communication Engineering, Chonnam National University) ;
  • Dong Yeong Kim (Dept, of ICT Convergence System Engineering and Electronic Communication Engineering, Chonnam National University) ;
  • Je Won Park (Dept, of ICT Convergence System Engineering and Electronic Communication Engineering, Chonnam National University) ;
  • Shin Wook Kim (Dept, of ICT Convergence System Engineering and Electronic Communication Engineering, Chonnam National University) ;
  • Chae Hyuk Lim (Chonnam National University) ;
  • So won Kim (Chonnam National University) ;
  • Hyeona Seo (Chonnam National University) ;
  • Ju Won Kim (Chonnam National University) ;
  • Hye Rin Lee (Chonnam National University) ;
  • Jeong Hyeon Yun (Chonnam National University) ;
  • Young-Woo Lee (Department of Computer Information and Communication Engineering in Chonnam National University) ;
  • Hyoung-Jin Joe (Department of Mechanical and Aerospace Engineering, University of Central Florida) ;
  • Myoung Jin Lee (Dept, of ICT Convergence System Engineering and Electronic Communication Engineering, Chonnam National University)
  • Received : 2023.12.05
  • Accepted : 2023.12.27
  • Published : 2023.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

As the cell spacing decreases during the scaling process of DRAM(Dynamic Random Access Memory), the reduction in STI(Shallow Trench Isolation) thickness leads to an increase in sub-threshold leakage due to the passing word line effect. The increase in sub-threshold leakage current caused by the voltage applied to adjacent passing word lines affects the data retention time and increases the number of refresh operations, thereby contributing to higher power consumption in DRAM. In this paper, we identify the causes of the passing word line effect through TCAD Simulation. As a result, we confirm the DRAM operational conditions under which the passing word line effect occurs, and observe that this effect alters the proportion of the total leakage current attributable to different causes. Through this, we recognize the necessity to consider not only leakage currents due to GIDL(Gate Induced Drain Leakage) but also sub-threshold leakage currents, providing guidance for improving DRAM structure.

DRAM(Dynamic Random Access Memory) 스케일링 과정에서 발생하는 셀간 거리의 감소에 따라 STI(Shallow Trench Isolation)두께 감소는 문턱이하 누설이 증가되는 패싱워드라인 효과를 유발한다. 인접한 패싱워드라인에 인가된 전압으로 인한 문턱이하누설 전류의 증가는 데이터 보존시간에 영향을 주며, 리프레시의 동작 횟수가 증가되어 DRAM의 소비 전력을 증가시키는 요인이 된다. 본 논문에서는 TCAD Simulation을 통해 패싱워드라인 효과에 대한 원인을 확인한다. 결과적으로, 패싱워드라인 효과가 발생하는 DRAM 동작상황을 확인하고, 이때 패싱워드라인 효과로 인해 전체 누설전류의 원인에 따른 비중이 달라지는 것을 확인하였다. 이를 통해, GIDL(Gate Induced Drain Leakage)에 의한 누설전류뿐만 아니라 문턱이하 누설전류를 고려의 필요성을 확인하며 이에 따른 DRAM 구조의 개선 방향의 지침이 될 수 있다.

Keywords

Acknowledgement

This research was supported by "Regional Innovation Strategy (RIS)" through the National Research Foundation of Korea(NRF) funded by the Ministry of Education(MOE)(2021RIS-002). The EDA tool was supported by the IC Design Education Center (IDEC), South Korea.

References

  1. M. J. Lee, K. W. Park, "A mechanism for dependence of refresh time on data pattern in DRAM," IEEE Electron Device Lett., vol.31, no.2, pp.168-170, 2010. DOI: 10.1109/LED.2009.2038243 
  2. M. J. Lee, "A sensing noise compensation bit line sense amplifier for low voltage applications," IEEE J. Solid-State Circuits, vol.46, no.3, pp.690-694, 2011. DOI: 10.1109/JSSC.2010.2102570 
  3. M. T. Bohr, "Nanotechnology goals and challenges for electronic applications," in IEEE Transactions on Nanotechnology, vol.1, no.1, pp. 56-62, 2002. DOI: 10.1109/TNANO.2002.1005426 
  4. T. Hamamoto, S. Sugiura and S. Sawada, "On the retention time distribution of dynamic random access memory (DRAM)," in IEEE Transactions on Electron Devices, vol.45, no.6, pp.1300-1309, 1998. DOI: 10.1109/16.678551 
  5. A. Spessot and H. Oh, "1T-1C Dynamic Random Access Memory Status, Challenges, and Prospects," in IEEE Transactions on Electron Devices, vol.67, no.4, pp.1382-1393, 2020. DOI: 10.1109/TED.2020.2963911 
  6. J. H. Park et al., "Row Hammer Reduction Using a Buried Insulator in a Buried Channel Array Transistor," in IEEE Transactions on Electron Devices, vol.69, no.12, pp.6710-6716, 2022. DOI: 10.1109/TED.2022.3215931 
  7. Y. Sun, X. Liu, N. Wang, J. Jeon, B. Wu and K. Cao, "Trap-Assisted Passing Word Line Leakage and Variable Retention Time in DRAM," 2021 IEEE 4th International Conference on Electronics Technology (ICET), Chengdu, China, 2021, pp. 338-341 DOI: 10.1109/ICET51757.2021.9451059 
  8. S. K. Gautam, S. K. Manhas, A. Kumar and M. Pakala, "Mitigating the Passing Word Line Induced Soft Errors in Saddle Fin DRAM," in IEEE Transactions on Electron Devices, vol.67, no.4, pp. 1902-1905, 2020. DOI: 10.1109/TED.2020.2975758 
  9. E. P. Vandamme, P. Jansen and L. Deferm, "Modeling the subthreshold swing in MOSFET's," in IEEE Electron Device Letters, vol.18, no.8, pp.369-371, 1997. DOI: 10.1109/55.605442 
  10. D. J. Wouters, J. P. Colinge, and H. E. Maes, "Subthreshold slope in thin-film SOI MOSFETs," IEEE Trans. Electron Devices, vol.37, pp.2022-2033, 1990. DOI: 10.1109/16.57165