• Title/Summary/Keyword: Memories

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An interpolation 1-D kernel with quadratic polynomials

  • Ozawa, Kazuhiro;Aikawa, Naoyuki;Sato, Masamitsu
    • Proceedings of the IEEK Conference
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    • 2000.07b
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    • pp.563-566
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    • 2000
  • Sampling rate conversion widely used in subband coding, A/D and D/A transitions etc. is an important techniques Nyquist filters and the filter banks have been used for the sampling converter. However, they need many memories and, whenever the sampling rate is changed, it is necessary to design filters. So the objective of this paper is to present a new kernel that is quick to evaluate and has a good stopband performance.

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Study on Task Scheduling for Parallel Processing of Nested Loops (다중 루프문의 병렬처리를 위한 타스크 스케줄링에 관한 연구)

  • 허정연;손윤구
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.29B no.1
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    • pp.11-17
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    • 1992
  • This paper is to propose an analytical queuing model for parallel processing of sequential program with nested loops. The analytical results are compared with the results from the implemented multiprocessor system composed of four intel 8088 microprocessor, eight 2KB shared common memories, and a hardware token ring. At results, this study shows that the processed results are almost similar in proposed analytical model and real system. Proposed analytical model can be applied to evaluate parallel processing of sequential program with nested loops.

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Synthesis of GBSB Neural Associative Memories Using GEVP (GEVP를 이용한 GBSB 연상 메모리의 설계)

  • Park, Yon-Mook;Park, Joo-Young
    • Proceedings of the KIEE Conference
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    • 1999.07g
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    • pp.2872-2875
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    • 1999
  • 본 논문은 주어진 적합한 이진 패턴들의 집합이 점근적으로 안정한 평형점들로써 저장되는 최적으로 성능을 갖는 GBSB (generalized brain-state-in-a-box)의 설계가 고려된다. GBSB 모델의 정성적 특성에 기초하여, 설계 문제가 제약 조건을 가한 최적화 문제로 공식화된다. 다음으로, 우리는 이 문제를 GEVP (generalized eigenvalue Problem)라고 불리는 최적화 문제로 변환한다. 제안된 방법을 예증하기 위함과 기존의 방법과의 비교를 위해서 설계 예제가 주어진다.

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Recommendable ecology forest-mountain areas (기획특집: 가볼만한 생태산촌)

  • Lee, Jae-Myun
    • Journal of the Korean Professional Engineers Association
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    • v.43 no.5
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    • pp.21-24
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    • 2010
  • The development of the mountain areas is the economic solution to the forest-mountain region that is becoming more hollw by the day. It can also be said as providing a rest area for those that live in the cities who long for their child-hood memories. This development will bring the vitalization of the regional economy and the balanced development of the national land planning. In order to bring the continuous development of the mountain areas, educating a dedicated professional forest-mountain expert is a must.

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IARC Carcinogenicity Assessment for 2-Bromopropane: 28 Years after Outbreak of Reproductive Toxicity (집단생식독성 발생 28년 후 원인물질 2-bromopropane에 대한 IARC 발암성평가)

  • Il Je Yu
    • Journal of Korean Society of Occupational and Environmental Hygiene
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    • v.33 no.1
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    • pp.1-2
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    • 2023
  • 2-Bromopropane, a causative chemical that caused the outbreak of reproductive toxicity 28 years ago, was classified as Group 2A in the recently held IARC monograph 133 meeting. Korean research data were used as supporting data in the carcinogenicity evaluation of 2-bromopropane and other carcinogens. I would like to share my memories with the researchers at the Occupational Safety and Health Research Institute who worked hard to identify the cause.

A New Buffer Management Scheme using Weighted Dynamic Threshold for QoS Support in Fast Packet Switches with Shared Memories (공유 메모리형 패킷 교환기의 QoS 기능 지원을 위한 가중형 동적 임계치를 이용한 버퍼 관리기법에 관한 연구)

  • Kim Chang-Won;Kim Young-Beom
    • Journal of the Institute of Convergence Signal Processing
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    • v.7 no.3
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    • pp.136-142
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    • 2006
  • Existing buffer management schemes for shared-memory output queueing switches can be classified into two types: In the first type, some constant amount of memory space is guaranteed to each virtual queue using static queue thresholds. The static threshold method (ST) belongs to this type. On the other hand, the second type of approach tries to maximize the buffer utilization in 머 locating buffer memories. The complete sharing (CS) method is classified into this type. In the case of CS, it is very hard to protect regular traffic from mis-behaving traffic flows while in the case of ST the thresholds can not be adjusted according to varying traffic conditions. In this paper, we propose a new buffer management method called weighted dynamic thresholds (WDT) which can process packet flows based on loss priorities for quality-of-service (QoS) functionalities with fairly high memory utilization factors. We verified the performance of the proposed scheme through computer simulations.

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A Design Methodology for CNN-based Associative Memories (연상 메모리 기능을 수행하는 셀룰라 신경망의 설계 방법론)

  • Park, Yon-Mook;Kim, Hye-Yeon;Park, Joo-Young;Lee, Seong-Whan
    • Journal of KIISE:Software and Applications
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    • v.27 no.5
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    • pp.463-472
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    • 2000
  • In this paper, we consider the problem of realizing associative memories via cellular neural network(CNN). After introducing qualitative properties of the CNN model, we formulate the synthesis of CNN that can store given binary vectors with optimal performance as a constrained optimization problem. Next, we observe that this problem's constraints can be transformed into simple inequalities involving linear matrix inequalities(LMIs). Finally, we reformulate the synthesis problem as a generalized eigenvalue problem(GEVP), which can be efficiently solved by recently developed interior point methods. Proposed method can be applied to both space varying template CNNs and space-invariant template CNNs. The validity of the proposed approach is illustrated by design examples.

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Si-Containing Nanostructures for Energy-Storage, Sub-10 nm Lithography, and Nonvolatile Memory Applications

  • Jeong, Yeon-Sik
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.08a
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    • pp.108-109
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    • 2012
  • This talk will begin with the demonstration of facile synthesis of silicon nanostructures using the magnesiothermic reduction on silica nanostructures prepared via self-assembly, which will be followed by the characterization results of their performance for energy storage. This talk will also report the fabrication and characterization of highly porous, stretchable, and conductive polymer nanocomposites embedded with carbon nanotubes (CNTs) for application in flexible lithium-ion batteries. It will be presented that the porous CNT-embedded PDMS nanocomposites are capable of good electrochemical performance with mechanical flexibility, suggesting these nanocomposites could be outstanding anode candidates for use in flexible lithium-ion batteries. Directed self-assembly (DSA) of block copolymers (BCPs) can generate uniform and periodic patterns within guiding templates, and has been one of the promising nanofabrication methodologies for resolving the resolution limit of optical lithography. BCP self-assembly processing is scalable and of low cost, and is well-suited for integration with existing semiconductor manufacturing techniques. This talk will introduce recent research results (of my research group) on the self-assembly of Si-containing block copolymers for the achievement of sub-10 nm resolution, fast pattern generation, transfer-printing capability onto nonplanar substrates, and device applications for nonvolatile memories. An extraordinarily facile nanofabrication approach that enables sub-10 nm resolutions through the synergic combination of nanotransfer printing (nTP) and DSA of block copolymers is also introduced. This simple printing method can be applied on oxides, metals, polymers, and non-planar substrates without pretreatments. This talk will also report the direct formation of ordered memristor nanostructures on metal and graphene electrodes by the self-assembly of Si-containing BCPs. This approach offers a practical pathway to fabricate high-density resistive memory devices without using high-cost lithography and pattern-transfer processes. Finally, this talk will present a novel approach that can relieve the power consumption issue of phase-change memories by incorporating a thin $SiO_x$ layer formed by BCP self-assembly, which locally blocks the contact between a heater electrode and a phase-change material and reduces the phase-change volume. The writing current decreases by 5 times (corresponding to a power reduction of 1/20) as the occupying area fraction of $SiO_x$ nanostructures varies.

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Programmable Memory BIST for Embedded Memory (내장 메모리를 위한 프로그램 가능한 자체 테스트)

  • Hong, Won-Gi;Chang, Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.12
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    • pp.61-70
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    • 2007
  • The density of Memory has been increased by great challenge for memory technology. Therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip (SOC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. Proposed design doesn't need controls from outside environment, because it integrates into memory. In general, there are a variety of memory modules in SOC, and it is not possible to test all of them with a single algorithm. Thus, the proposed scheme supports the various memory testing process. Moreover, it is able to At-Speed test in a memory module. consequently, the proposed is more efficient in terms of test cost and test data to be applied.

Comparative investigation of endurance and bias temperature instability characteristics in metal-Al2O3-nitride-oxide-semiconductor (MANOS) and semiconductor-oxide-nitride-oxide-semiconductor (SONOS) charge trap flash memory

  • Kim, Dae Hwan;Park, Sungwook;Seo, Yujeong;Kim, Tae Geun;Kim, Dong Myong;Cho, Il Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.4
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    • pp.449-457
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    • 2012
  • The program/erase (P/E) cyclic endurances including bias temperature instability (BTI) behaviors of Metal-$Al_2O_3$-Nitride-Oxide-Semiconductor (MANOS) memories are investigated in comparison with those of Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) memories. In terms of BTI behaviors, the SONOS power-law exponent n is ~0.3 independent of the P/E cycle and the temperature in the case of programmed cell, and 0.36~0.66 sensitive to the temperature in case of erased cell. Physical mechanisms are observed with thermally activated $h^*$ diffusion-induced Si/$SiO_2$ interface trap ($N_{IT}$) curing and Poole-Frenkel emission of holes trapped in border trap in the bottom oxide ($N_{OT}$). In terms of the BTI behavior in MANOS memory cells, the power-law exponent is n=0.4~0.9 in the programmed cell and n=0.65~1.2 in the erased cell, which means that the power law is strong function of the number of P/E cycles, not of the temperature. Related mechanism is can be explained by the competition between the cycle-induced degradation of P/E efficiency and the temperature-controlled $h^*$ diffusion followed by $N_{IT}$ passivation.