• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.256-256
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• 2009

This paper presents a proper condition to achieve above 17 % conversion efficiency using PC1D simulator. Crystalline silicon wafer with thickness of $240{\mu}m$ was used as a starting material. Various efficiency influencing parameters such as rear surface recombination velocity and minority carrier diffusion length in the base region, front surface recombination velocity, junction depth and doping concentration in the Emitter layer. Among the investigated variables, we learn that 2nd doping concentration as a key factor to achieve conversion efficiency higher than 17 %.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.63-64
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• 2006

Here we present detailed simulation results of trench field stop IGBTs. Besides the reduced on-state voltage drop there is also an Increase of forward blocking voltage. A trench gate IGBT has low on-state voltage drop mainly due to the removal of the JFET region and a field stop IGBT has high forward blocking voltages due to the trapezoidal field distribution under blocking condition. We have simulated the static characteristics of TIGBT with field stop technology by 2D simulator(MEDICI). The simulated result of forward blocking voltage and on-state voltage drop is about 1,408V and 1.3V respectively at $110{\mu}m$ N-drift thickness.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.131-139
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• 1996

Inthis apper wa analyzed the channel-hot-electron programming characteristics of the single-poly EEPROM with different control gate and drain structures. The single-poly EEPROM uses the p$^{+}$/n$^{+}$-diffusion in the n-well as a control gate instead of the second poly-silicon. The program and erase characteristics of the single-poly EEPROM were verified using the two-dimensional device simulator, MEDICI. The single-poly EEPROM was fabricated using 0.8$\mu$m ASIC CMOS process, and its CHE programming characteristics were measured using HP4155 parameteric analyzer and HP8110 pulse gnerator. Especially we investigated the CHE programming characteristics of the single-poly EEPROM with the p$^{+}$-diffusion or n$^{+}$-diffusion in the n-well as a control gate and the LDD or single-drain structure. The single-poly EEPROM with p$^{+}$-diffusion in the n-well as a control gate and single-drain structure was programmed to about VT$\thickapprox$5V with VDS=6V, VCG=12V(1ms pulse width).th).

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.239-242
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• 1999

In this paper, we report the process/device design of high-speed, high-voltage SOI smart power IC for mobile communication system, high-speed HDD system and the electronic control system of automobiles. The high voltage LDMOS with 70V breakdown voltage under 0.8${\mu}{\textrm}{m}$ design rule, the high voltage bipolar with 40V breakdown voltage for analog signal processing, the high speed bipolar with cut-off frequency over 20㎓ and LDD NMOS for high density were proposed and simulated on a single chip by the simulator DIOS and DESSIS. And we extracted the process/device parameters of the simulated devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.228-233
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• 2007

Core technologies for integrating hydrogen gas sensor were investigated. In this study, the thermally isolated micro-hot-plate with areas of $100{\times}100-260{\times}260{\mu}m^2$ was fabricated by utilizing surface micromachining technique that provides better manufacturing yield than bulk micromachining counterpart. The optimum design of the sensor was peformed by analyzing the thermal profile of the structure obtained from a ANSYS simulator. The 400-nm-thick polysilicon films doped with phosphorus, the 300-nm-thick aluminum films, and the 200-nm-thick $SnO_2$(or ZnO)films were used as the micro-heater material, the temperature sensor material, and the gas sensitive material, respectively. The experimental results show that the developed gas sensors can detect $H_2$ concentration as low as 1 ppm.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1059-1060
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• 2006

In this study, vibration mode multilayer piezoelectric transformer was designed and thickness simulated using ANSYS of finite element method simulator for investigating its optimum conditions ist. As a results, resonant frequency was decreased with the increase of output layer thickness, Output voltage, maximum displacement and maximum stress at 0.34mm thickness transformer were 228.1 V, $0.42{\mu}m,\;8.78[N/m^2]$ respectively.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1621-1623
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• 1997

The breakdown voltage of SOI RESURF (REduce SURface Field) diode using a SIPOS (Semi Insulating POlycrystalline Silicon) layer is verified in terms of n-drift layer length and surface oxide thickness by device simulator MEDICI, and compared with conventional SOI RESURF diode. Increasing the n-drift layer length, the breakdown voltage of SOI RESURF diode using the SIPOS layer have increased and saturated at $8{\mu}m$. And it has decreased with increasing the surface oxide thickness.

• 한국항공운항학회:학술대회논문집
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• 2015.11a
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• pp.183-185
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• 2015

A-SMGCS는 외부로부터 비행계획정보, 레이더 정보 및 기상정보를 수신하여 경로, 안내, 감시 및 항공등화 제어 기능을 수행하는데, 이러한 기능을 검정하기 위한 시뮬레이터는 기초자료 준비, 기상 시나리오 생성, 이벤트 시나리오 생성 및 항적자료 생성 등의 4가지 기능으로 구성되어 가상의 정보를 자동으로 생성하게 된다. 생성된 정보는 A-SMGCS에서 수신하여 그 정보를 바탕으로 각각의 기능들을 실행하게 되고, 그 실행 상태는 A-SMGCS HMI에 모니터링 된다. 그러므로 시뮬레이터에서 생성되는 가상의 시나리오들은 실제 공항에서 발생하거나 예측되는 모든 경우의 상황을 A-SMGCS에 제공하여 정확한 검정을 할 수 있도록 지원함으로써 A-SMGCS의 성능을 한층 더 향상시킬 수 있을 것이다. 따라서 본 논문에서는 이러한 효과가 기대되는 시뮬레이터의 기능과 연동관계를 정리하여 최적의 시뮬레이터를 제작할 수 있는 방법에 대한 연구를 실시하였다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.60-68
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• 1993

Thw VLSI device of submicron level trends to have a low level of reliability because of hot carriers which are caused by short channel effects and which do not appear in a long-channel MOSFET operated in 5V. In order to minimize the generation of hot carrier, much research has been made into various types of drain structures. This study has suggested CG MOSFET (Concaved Gate MOSFET) as new drain structure and compared its electrical characteristics with those of the conventional MOSFET and LDD-structured MOSFET by making use of a simulation method. These three device were assumed to be produced by the LOCOS process and a computer-based analysis(PISCES-2B simulator) was carried out to verify the hot electron-resistant behaviours of the devices. In the present simulation, the channel length of these devises was 1.0$\mu$m and their DC characteristics, such as VS1DT-IS1DT curves, gate and substrate current, potential contours, breakdown voltage and electric field were compared with one another.

• Journal of information and communication convergence engineering
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• v.9 no.1
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• pp.11-15
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• 2011

A Differential line inductor is proposed for a differential power amplifier. The proposed differential line inductor is composed of two conventional line inductors rearranged to make the current direction of the two line inductors identical. The proposed line inductor is simulated with a 2.5-D and a 3-D EM simulator to verify its feasibility with the substrate information in a 0.18-${\mu}m$ RF CMOS process. The inductances of various line inductors implemented with printed circuit boards were measured. The feasibility of the proposed line inductor was successfully demonstrated.