• Title/Summary/Keyword: MU simulator

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Breakdown and On-state characteristics of the Multi-RESURF SOI LDMOSFET (Epi층의 농도 및 두께 변화에 따른 Multi-RESURF SOI LDMOSFET의 특성분석)

  • Kim, Hyoung-Woo;Kim, Sang-Cheol;Seo, Kil-Su;Kim, Nam-Kyun;Kim, Eun-Dong
    • Proceedings of the KIEE Conference
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    • 2002.07c
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    • pp.1578-1580
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    • 2002
  • The breakdown and on-state characteristics of the multi-RESURF SOI LDMOSFET is presented. P-/n-epi layer thickness and doping concentration is varied from $2{\mu}m{\sim}5{\mu}m$ and $1{\times}10^{15}/cm^3{\sim}9{\times}10^{15}/cm^3$ to obtain optimum breakdown voltage and on-resistance. The breakdown and on-state characteristics of the device is verified by two-dimensional process simulator ATHENA and device simulator ATLAS.

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Investigation of Optimal Channel Doping Concentration for 0.1\;μm SOI-MOSFET by Process and Device Simulation ([ 0.1\;μm ] SOI-MOSFET의 적정 채널도핑농도에 관한 시뮬레이션 연구)

  • Choe, Kwang-Su
    • Korean Journal of Materials Research
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    • v.18 no.5
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    • pp.272-276
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    • 2008
  • In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.

An Optimization of Cast poly-Si solar cell using a PC1O Simulator (PC1D를 이용한 cast poly-Si 태양전지의 최적화)

  • Lee, Su-Eun;Lee, In;Ryu, Chang-Wan;Yi, Ju-Sin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.11a
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    • pp.553-556
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    • 1999
  • This paper presents a proper condition to achieve above 19 % conversion efficiency using PC1D simulator. Cast poly-Si wafers with resistivity of 1 $\Omega$-cm and thickness of 250 ${\mu}{\textrm}{m}$ were used as a starting material. Various efficiency influencing parameters such as rear surface recombination velocity and minority carrier diffusion length in the base region, front surface recombination velocity, junction depth and doping concentration in the Emitter layer, BSF thickness and doping concentration were investigated. Optimized cell parameters were given as rear surface recombination of 1000 cm/s, minority carrier diffusion length in the base region 200 ${\mu}{\textrm}{m}$, front surface recombination velocity 100 cnt/s, sheet resistivity of emitter layer 100 $\Omega$/$\square$, BSF thickness 5 ${\mu}{\textrm}{m}$, doping concentration 5$\times$10$^{19}$ cm$^3$ . Among the investigated variables, we learn that a diffusion length of base layer acts as a key factor to achieve conversion efficiency higher than 19 %. Further details of simulation parameters and their effects to cell characteristics are discussed in this paper.

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Effects of Lightning Surges on the Life of ZnO Varistors (뇌서지가 ZnO바리스터에 미치는 영향)

  • Lee, Bong;Lee, Su-Bong;Kang, Sung-Man;Lee, Bok-Hee
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.55 no.5
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    • pp.257-262
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    • 2006
  • To evaluate the change in protective levels of zinc oxide (ZnO) varistors after the surge absorption, this paper investigated the effects of the number of injection and amplitude of lightning surges on the life of ZnO varistors for low voltages. Leakage currents flowing through ZnO varistors subjected to the $8/20{\mu}s$ impulse currents under 60 Hz AC voltages were measured. The surge simulator system ECAT that can generate $8/20{\mu}s$ impulse currents with a peak short-circuit of 5 $[kA_p]$ was used. The ZnO varistor leakage current increases with exposure to impulse current, and the number of injection of $8/20{\mu}s$ impulse currents to breakdown was inversely proportional to the amplitude of the test current. Behaviors of ZnO varistor leakage currents were strongly dependent on the number of injection and amplitude of $8/20{\mu}s$ impulse currents. ZnO varistors degrade gradually when subjected to impulse current, and the resistive leakage current flowing through ZnO varistors subjected to the $8/20{\mu}s$ impulse currents under 60 Hz AC voltages was significantly increased after a certain number of injection that is dependent on the amplitude of the test impulse current. As a result, the life of ZnO varistors mainly depends on the amplitude and occurrence frequency of lightning surges.

A Study on the Integrated System and Sensitivity Analysis for Line Capacity Calculation Model (선로용량 계산 모델의 통합과 통합 민감도 분석 체계에 관한 연구)

  • Kim, Mu-Ryong;Kim, Han-Sin;Lee, Chang-Ho;Kim, Bong-Seon;Kim, Dong-Hui;Hong, Sun-Heum
    • Proceedings of the Safety Management and Science Conference
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    • 2005.11a
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    • pp.30-39
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    • 2005
  • Line capacity calculation has been used to determine optimum efficiency and safe train service for train scheduling plan and investment priority order throughout detecting bottleneck section. Because of some problems of Yamagisi and UIC methods for line capacity calculation, developing of the method of line capacity calculation and evaluation for the Korea circumstance is important. This paper deals with the integrated system of TPS(Train Performance Simulator), PES(Parameter Evaluation Simulator), LCS (Line Capacity Simulator) and sensitivity analysis for line capacity calculation model.

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Characteristics analysis of Sub-50nm Double Gate MOSFET (Sub-50nm Double Gate MOSFET의 특성 분석)

  • 김근호;고석웅;이종인;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2002.11a
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    • pp.486-489
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    • 2002
  • In this paper, we have investigated characteristics of sub-50nm double gate MOSFET. From I-V characteristics, we obtained =510$\mu$A/${\mu}{\textrm}{m}$ at VMG=VDS=1.5V and VSG=3.0V. Then, the transconductance is 111$\mu$A/V, subthreshold slope is 86mV/dec and DIBL (Drain Induced Barrier Lowering) is 51.3mV. Also, we have presented that TCAD simulator is suitable for device simulation.

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Study on the application of a realtime simulator to the development of a controller for a space thermal environment chamber (실시간 플랜트 시뮬레이터를 이용한 우주 열환경 챔버 제어기 개발에 관한 연구)

  • Jung, Mu-Jin;Shin, Young-Gy;Choi, Seok-Weon;Moon, Guee-Won;Seo, Hee-Jun;Lee, Sang-Hoon;Cho, Hyok-Jin
    • Proceedings of the KSME Conference
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    • 2003.11a
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    • pp.216-221
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    • 2003
  • A thermal vacuum chamber is mainly used to simulate thermal environments of a test satellite in satellite orbits in which daily temperature variations range from 80K to above 400K depending on solar radiation under the vacuum below $10^{-4}$ torr. The test facility is quite complex and consists of expensive parts. So any modification of control software is discouraged in fear of unexpected system failure. The purpose of this study is to develop a realtime dynamics model of the thermal vacuum chamber in view of controller design and simulate its electrical inputs and outputs for interface with a PLC (programmable logic controller). A PLC program that was used in the thermal vacuum chamber is applied to the realtime simulator. The realized simulator dynamics is found to be quite similar to that of the thermal vacuum chamber and serve to an appropriate plant to verify the control performance of a programmed PLC.

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A Study on Improvement Latch-up immunity and Triple Well formation in Deep Submicron CMOS devices (Deep Submicron급 CMOS 디바이스에서 Triple Well 형성과 래치업 면역 향상에 관한 연구)

  • 홍성표;전현성;강효영;윤석범;오환술
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.9
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    • pp.54-61
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    • 1998
  • A new Triple well structure is proposed for improved latch-up immunity at deep submicron CMOS device. Optimum latch-up immunity process condition is established and analyzed with varying ion implantation energy and amount of dose and also compared conventional twin well structure. Doping profile and structure are investigated using ATHENA which is process simulator, and then latch-up current is calculated using ATLAS which is device simulator. Two types of different process are affected by latch-up characteristics and shape of doping profiles. Finally, we obtained the best latch-up immunity with 2.5[mA/${\mu}{m}$] trigger current using 2.5 MeV implantation energy and 1$\times$10$^{14}$ [cm$^{-2}$ ] dose at p-well

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