• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 춘계학술대회 논문집 에너지변화시스템부문
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• pp.125-130
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• 2009

This paper reviews the characteristics technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• 한국전기전자재료학회논문지
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• 제33권4호
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• pp.255-262
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• 2020

Grain boundaries play a major role in determining device performance, particularly of polysilicon-based photodetectors. Through the post-annealing of as-deposited polysilicon and then, the analysis of electric behavior for a metal-polysilicon-metal (MSM) photodetector, we were able to identify the influence of grain boundaries. A modified model of polysilicon grain boundaries in the MSM structure is presented, which uses a crystalline-interfacial layer-SiO_x layer- interfacial layer-crystalline system that is similar to the Si-SiO₂ system in MOS device. Hydrogen passivation was achieved through a hydrogen ion implantation process and was used to passivate the defects at both interfacial layers. The thin SiO_x layer at the grain boundary can enhance the photosensitivity of an MSM photodetector by decreasing the dark current and increasing the light absorption.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기물성,응용부문
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• pp.159-160
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• 2002

본 논문에서는 반도체 응용부문 중 그 활용도가 높은 MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor)의 새로운 구조를 제안하였다. 제안한 소자를 가지고 전자회로의 구성할 때 인접 디바이스들과 연계되어 발생되는 래치 업(latch-up)을 근본적으로 제거하고, 개별소자의 완전한 절연을 실현하였으며 누설전류 또한 제거된다. 이는 SOI기판 위에 벌크실리콘 공정을 이용하여 구현된다. 즉, 소자 양옆의 트랜치 웰(Trench-well)과 SOI 기판의 절연층으로 소자의 독립성을 지켜준다. 또한 게이트 절연층을 트랜치 구조로 기존 MOS구조의 채널 부분에 위치시키고 드레인과 소스를 위치시켜 자연적으로 자기정렬이 되어진다. 이와 같은 과정으로 게이트-소스, 게이트-드레인 기생 커패시터의 효과를 현저히 줄일 수 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 학술대회 및 기술세미나 논문집 디스플레이 광소자
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• pp.62-63
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• 2006

In this paper, the characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) fabricated on polymer substrates are investigated. The a-Si films was laser annealed by using a XeCl excimer laser and a four-mask-processed poly-Si TFT was fabricated with fully self-aligned top gate structure. The fabricated nMOS TFT showed field-effect mobility of $30cm2/V{\cdot}s$, on/off ratio of 105 and threshold voltage of 5 V.

• 전기전자학회논문지
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• 제23권2호
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• pp.454-460
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• 2019

In this paper, a watt-level 2.4-GHz RFCMOS linear power amplifier (PA) with pre-distortion method using variable capacitance with respect to input power is demonstrated. The proposed structure is composed of a power detector and a MOS capacitor to improve the linearity of the PA. The pre-distortion based linearizer is embedded in the two-stage PA to compensate for the gain compression in the amplifier stages, it also improves the output P1dB by approximately 1 dB. The simulation results demonstrate a 1-dB gain compression power of 30.81 dBm at 2.4-GHz, and PAE is 29.24 % at the output P1dB point.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.105.3-105
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• 2001

In this paper, a current mode two-input maximum (Max) and minimum (Min) operations scheme, which is a useful building block for analog fuzzy inference systems, is presented. The Max and Min operations are incorporated in the same scheme with parallel processing. The proposed scheme comprises a MOS class AB/B configuration and current mirrors. Its simple structure can provide a high efficiency. The performance of the scheme exhibits a very sharp transfer characteristic and high accuracy. The proposed scheme achieves a high-speed operation and is suitable for real-time systems. The simulation results verifying the performances of the scheme are agreed with the expected values.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.355-358
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• 2004

In this work, N-LDMOSFET(Lateral Double diffused MOSFET) was designed and fabricated on SOI(Silicon-On-Insulator) substrate, for such applications as motor controllers and high voltage switches, fuel injection controller systems in automobile and SSR(Solid State Rexay)etc. The LDMOSFET was designed to overcome the floating body effects that appear in the conventional thick SOI MOS structure by adding p+ region in source region. Also, RESURF(Reduced SURface Field) structure was proposed in this work in order to reduce a large on-resistance of LDMOSFET when operated keeping high break down voltage. Breakdown voltage was 268v in off-state ($V_{GS}$=OV) at room temperature in $22{\mu}m$ drift length LDMOSFET. When 5V of $V_{GS}$ and 30V of $V_{DS}$ applied, the on resistance(Ron), the transcon ductance($G_m$) and the threshold voltage($V_T$) was 1.76k$\Omega$, 79.7uA/V and 1.85V respectively.

• 전자공학회논문지
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• 제50권2호
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• pp.134-139
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• 2013

UWB의 일종인 MBOA 무선통신 시스템에 내장하기 위한 광대역 RF 주파수 합성기를 $0.13{\mu}m$ 실리콘 CMOS 기술을 이용하여 설계하였다. 효율적인 MBOA 클록신호 생성을 위하여 낮은 주파수를 갖는 하위 밴드에서는 큰 배수로 주파수를 합성하고, 높은 주파수를 갖는 상위 밴드에서는 작은 배수로 주파수를 합성함으로서 VCO의 발진범위를 대폭 줄일 수 있는 새로운 방법을 적용하였다. 설계된 PLL 회로는 P-MOS 코어 구조의 VCO 및 수퍼 다이나믹 구조의 주파수 분할기를 사용하여 고속 및 광대역 동작 범위를 확보하였다.

• 전자공학회논문지A
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• 제33A권2호
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• pp.173-183
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• 1996

In this paper, a new structure that can do fault detection and location of digial logic circuits more efficiently using current testing techniques is proposed. In the conventional method, observation point for steady state power supply current was only one, but in the proposed method more fault classes are divided for fault detection and location through the ovservation of steady state power supply current at two points. Also, it is shown that this structure can be easily applied in detection of stuck-open fault which is not easy to do testing with conventional current testing techniques. In the presented mehtod, an extra trasnistor is used, and current path is made compulsorily in the CMOS circuits in which no current path can be established in steady state, then it can be known that stuck-open tault is in the MOS transistor on the considering current path, if this path disappears due to stuck-open fault. The validity and the effectiveness is shwon, thorugh the SPICE simulation of circuits with fault and the current path search experiment using current path search program based on transistor short model wirtten in C language on SUN sparc workstation.

• 센서학회지
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• 제17권1호
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• pp.41-52
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• 2008

In this paper, a circuit analysis of the complementary CMOS active pixel and readout circuit is carried out. Complementary pixel structure which is different from conventional 3TR APS structure is consist of photo diode, reset PMOS, several NMOSs and PMOSs sets for complementary signals. Photo diode is modelled with Medici device program. HSPICE was used to analyze the variation of the signal feature depending on light intensity using $0.5{\mu}M$ standard CMOS process. Simulation results show that the output signal range is from 0.8 V to 4.5 V. This signal range increased 135 % output dynamic range compared to conventional 3TR pixel in the condition of 5 V power supply.