• Title/Summary/Keyword: MFIS device

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Effect of ZrO2 Buffer Layers for Pt/Bi3.25La0.75Ti3O12/ZrO2/Si (MFIS)-FET Structures (Pt/Bi3.25La0.75Ti3O12/ZrO2/Si (MFIS)-FET 구조를 위한 ZrO2 Buffer Layer의 영향)

  • Kim, Kyoung-Tae;Kim, Chang-Il
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.5
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    • pp.439-444
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    • 2005
  • We investigated the structural and electrical properties of BLT films grown on Si covered with $ZrO_{2}$ buffer layer. The BLT thin film and $ZrO_{2}$ buffer layer were fabricated using a metalorganic decomposition method. The electrical properties of the MFIS structure were investigated by varying thickness of the $ZrO_{2}$ layer. AES and TEM show no interdiffusion and reaction that suppressed using the $ZrO_{2}$ film as a buffer layer The width of the memory window in the C-V curves for the MFIS structure decreased with increasing thickness of the $ZrO_{2}$ layer. It is considered that the memory window width of MFIS is not affected by remanent polarization. Leakage current density decreased by about four orders of magnitude after using $ZrO_{2}$ buffer layer. The results show that the $ZrO_{2}$ buffer layers are prospective candidates for applications in MFIS-FET memory devices.

Electrical Properties of Pt/$LiNbO_3$/AIN/Si(100) structures (Pt/$LiNbO_3$/AIN/Si(100) 구조의 전기적 특성)

  • 정순원;정상현;인용일;김광호
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.58-61
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    • 2001
  • Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

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Fabrications and properties of MFIS structure using AIN buffer layer (AIN 버퍼층을 사용한 MFIS 구조의 제작 및 특성)

  • 정순원;김용성;이남열;김진규;정상현;김광호;유병곤;이원재;유인규
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.29-32
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    • 2000
  • Meta1-ferroelectric-insulator-semiconductor(MFIS) devices using Pt/LiNbO$_{3}$/AIN/Si structure were successfully fabricated. AIN thin films were made into metal-insulator-semiconductor(MIS) devices by evaporating aluminum in a dot array on the film surface. The dielectric constant of the AIN film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V ) characteristic is 8. The gate leakage current density of MIS devices using a aluminum electrode showed the least value of 1$\times$10$^{-8A}$ $\textrm{cm}^2$ order at the electric field of 500㎸/cm. A typica] value of the dielectric constant of MFIS device was about 23 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 500㎸/cm was about 5.6$\times$ 10$^{13}$ $\Omega$.cmcm

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Fabrications and properties of MFIS capacitor using SiON buffer layer (SiON buffer layer를 이용한 MFIS Capacitor의 제작 및 특성)

  • 정상현;정순원;인용일;김광호
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.70-73
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    • 2001
  • MFIS(Metal-ferroelectric-insulator- semiconductor) structures using silicon oxynitride(SiON) buffer layers were fabricatied and demonstrated nonvolatile memory operations. Oxynitride(SiON) films have been formed on p-Si(100) by RTP(rapid thermal process) in O$_2$+N$_2$ ambient at 1100$^{\circ}C$. The gate leakage current density of Al/SiON/Si(100) capacitor was about the order of 10$\^$-8/ A/cm$^2$ at the range of ${\pm}$ 2.5 MV/cm. The C-V characteristics of Al/LiNbO$_3$/SiON/Si(100) capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 24. The memory window width was about 1.2V at the electric field of ${\pm}$300 kV/cm ranges.

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Electric Properties of MFIS Capacitors using Pt/LiNbO3/AlN/Si(100) Structure (Pt/LiNbO3/AlN/Si(100) 구조를 이용한 MFIS 커패시터의 전기적 특성)

  • Jung, Soon-Won;Kim, Kwang-Ho
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.17 no.12
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    • pp.1283-1288
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    • 2004
  • Metal-ferroelectric-insulator-semiconductor(WFIS) capacitors using rapid thermal annealed LiNbO$_3$/AlN/Si(100) structure were fabricated and demonstrated nonvolatile memory operations. The capacitors on highly doped Si wafer showed hysteresis behavior like a butterfly shape due to the ferroelectric nature of the LiNbO$_3$ films. The typical dielectric constant value of LiNbO$_3$ film in the MFIS device was about 27, The gate leakage current density of the MFIS capacitor was 10$^{-9}$ A/cm$^2$ order at the electric field of 500 kV/cm. The typical measured remnant polarization(2P$_{r}$) and coercive filed(Ec) values were about 1.2 $\mu$C/cm$^2$ and 120 kV/cm, respectively The ferroelectric capacitors showed no polarization degradation up to 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulses of 1 MHz. The switching charges degraded only by 10 % of their initial values after 4 days at room temperature.e.

Fabrications and Properties of MFIS Structures using high Dielectric AIN Insulating Layers for Nonvolatile Ferroelectric Memory (고유전율 AIN 절연층을 사용한 비휘발성 강유전체 메모리용 MFIS 구조의 제작 및 특성)

  • Jeong, Sun-Won;Kim, Gwang-Hui;Gu, Gyeong-Wan
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.11
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    • pp.765-770
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    • 2001
  • Metal-ferroelectric-insulator- semiconductor(MFTS) devices by using rapid thermal annealed (RTA) LiNbO$_3$/AIN/Si(100) structures were successfully fabricated and demonstrated nonvolatile memory operations. Metal-insulator-semiconductor(MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2 V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/$\textrm{cm}^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8 V, 50 % duty cycle) in the 500 kHz.

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Device characterization and Fabrication Issues for Ferroelectric Gate Field Effect Transistor Device

  • Yu, Byoung-Gon;You, In-Kyu;Lee, Won-Jae;Ryu, Sang-Ouk;Kim, Kwi-Dong;Yoon, Sung-Min;Cho, Seong-Mok;Lee, Nam-Yeal;Shin, Woong-Chul
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.2 no.3
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    • pp.213-225
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    • 2002
  • Metal-Ferroelectric- Insulator- Silicon (MFIS) structured field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate field effect transistor device were summarized in three sections. The choice of interlayer dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelectric thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell address schemes were also suggested.

Recent Development in Polymer Ferroelectric Field Effect Transistor Memory

  • Park, Youn-Jung;Jeong, Hee-June;Chang, Ji-Youn;Kang, Seok-Ju;Park, Cheol-Min
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.51-65
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    • 2008
  • The article presents the recent research development in polymer ferroelectric non-volatile memory. A brief overview is given of the history of ferroelectric memory and device architectures based on inorganic ferroelectric materials. Particular emphasis is made on device elements such as metal/ferroelectric/metal type capacitor, metal-ferroelectric-insulator-semiconductor (MFIS) and ferroelectric field effect transistor (FeFET) with ferroelectric poly(vinylidene fluoride) (PVDF) and its copolymers with trifluoroethylene (TrFE). In addition, various material and process issues for realization of polymer ferroelectric non-volatile memory are discussed, including the control of crystal polymorphs, film thickness, crystallization and crystal orientation and the unconventional patterning techniques.

Electrical Characteristics of Pt/SBT/${Ta_2}{O_5}/Si$ Structure for Non-Volatile Memory Device (비휘발성 메모리를 위한 Pt/SBT/${Ta_2}{O_5}/Si$ 구조의 전기적 특성에 관한 연구)

  • Park, Geon-Sang;Choe, Hun-Sang;Choe, In-Hun
    • Korean Journal of Materials Research
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    • v.10 no.3
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    • pp.199-203
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    • 2000
  • $Ta_2_O5$ and $Sr_0.8Bi_2.4Ta_2O_9$ films were deposited on p-type Si(100) substrates by a rf-magnetron sputtering and the metal organic decomposition (MOD), respectively.The electrical characteristics of the $Pt/SBT/Ta_2O_5/Si$ structure were obtained as the functions of $O_2$ gas flow ratio during the $Ta_2_O5$ sputtering and $Ta_2_O5$ thickness. And to certify the role of $Ta_2_O5$ as a buffer layer, the electrical characteristics of $Pt/SBT/Ta_2O_5/Si$ were compared. $Pt/SBT/Ta_2O_5/Si$ capacitor with 20% $O_2$ gas flow ratio during the $Ta_2_O5$ sputtering did now show typical C-V curve of metal/ferroelectric/insulator/semiconductor (MFIS) structure. The capacitor with 20% $O_2$ gas flow ratio during the $Ta_2_O5$ sputtering had the largest memory window. And the memory window was decreased as the $Ta_2_O5$ gas flow ratio during the $Ta_2_O5$ sputtering was increased to 40%, 60%. In the C-V characteristics of the $Pt/SBT/Ta_2O_5/Si$ capacitors with the different $Ta_2_O5$ thickness, the capacitor with 26nm thickness of $Ta_2_O5$ had the largest memory window. The C-V and leakage current characteristics of the Pt/SBT/Si structure were worse than those of $Pt/SBT/Ta_2O_5/Si$ structure. These results and Auger electron spectroscopy (AES) measurement showed that $Ta_2_O5$ films as a buffer layer tool a role to prevent from the formation of intermediate phase and interdiffusion between SBT and Si.

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Physical and Electrical Characteristics of SrBi$_2$Ta$_2$O$_9$ thin Films Etched with Inductively Coupled Plasma Reactive Ion Etching System (유도결합형 플라즈마 반응성 이온식각 장치를 이용한 SrBi$_2$Ta$_2$O$_9$ 박막의 물리적, 전기적 특성)

  • 권영석;심선일;김익수;김성일;김용태;김병호;최인훈
    • Journal of the Microelectronics and Packaging Society
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    • v.9 no.4
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    • pp.11-16
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    • 2002
  • In this study, the dry etching characteristics of $SrBi_2Ta_2O_9$ (SBT) thin films were investigated by using ICP-RIE (inductively coupled plasma-reactive ion etching). The etching damage and degradation were analyzed with XPS (X-ray photoelectron spectroscopy) and C-V (Capacitance-Voltage) measurement. The etching rate increased with increasing the ICP power and the capacitively coupled plasma (CCP) power. The etch rate of 900$\AA$/min was obtained with 700 W of ICP power and 200 W of CCP power. The main problem of dry etching is the degradation of the ferroelectric material. The damage-free etching characteristics were obtained with the $Ar/C1_2/CHF_3$ gas mixture of 20/14/2 when the ICP power and CCP power were biased at 700 W and 200 W, respectively. The experimental results show that the dry etching process with ICP-RIE is applicable to the fabrication of the single transistor type ferroelectric memory device.

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