• 제목/요약/키워드: MEMS device

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Packaging MEMS, The Great Challenge of the $21^{st}$ Century

  • Bauer, Charles-E.
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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    • pp.29-33
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    • 2000
  • MEMS, Micro Electro-Mechanical Systems, present one of the greatest advanced packaging challenges of the next decade. Historically hybrid technology, generally thick film, provided sensors and actuators while integrated circuit technologies provided the microelectronics for interpretation and control of the sensor input and actuator output. Brought together in MEMS these technical fields create new opportunities for miniaturization and performance. Integrated circuit processing technologies combined with hybrid design systems yield innovative sensors and actuators for a variety of applications from single crystal silicon wafers. MEMS packages, far more simple in principle than today's electronic packages, provide only physical protection to the devices they house. However, they cannot interfere with the function of the devices and often must actually facilitate the performance of the device. For example, a pressure transducer may need to be open to atmospheric pressure on one side of the detector yet protected from contamination and blockage. Similarly, an optical device requires protection from contamination without optical attenuation or distortion being introduced. Despite impediments such as package standardization and complexity, MEMS markets expect to double by 2003 to more than $9 billion, largely driven by micro-fluidic applications in the medical arena. Like the semiconductor industry before it. MEMS present many diverse demands on the advanced packaging engineering community. With focused effort, particularly on standards and packaging process efficiency. MEMS may offer the greatest opportunity for technical advancement as well as profitability in advanced packaging in the first decade of the 21st century! This paper explores MEMS packaging opportunities and reviews specific technical challenges to be met.

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비전도성 에폭시를 사용한 RF-MEMS 소자의 웨이퍼 레벨 밀봉 실장 특성

  • 박윤권;이덕중;박흥우;송인상;박정호;김철주;주병권
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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    • pp.129-133
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    • 2001
  • In this paper, hermetic sealing was studied fur wafer level packaging of the MEMS devices. With the flip-chip bonding method, this B-stage epoxy sealing will be profit to MEMS device sealing and further more RF-MEMS device sealing. B-stage epoxy can be cured 2-step and hermetic sealing can be obtained. After defining $500{\mu}{\textrm}{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was then aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line were maintained during the sealing process. The height of the seal-line was controlled within $\pm0.6${\mu}{\textrm}{m}$ and the strength was measured to about 20MPa by pull test. The leak rate of the epoxy was about $10^7$ cc/sec from the leak test.

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대면적 플랫폼을 갖는 Probe-based Storage Device(PSD)용 정전형 2축 MEMS 스테이지 (Electrostatic 2-axis MEMS Stage with a Large Area Platform for Probe-based Storage Devices)

  • 정일진;전종업
    • 한국정밀공학회지
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    • 제23권9호
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    • pp.179-189
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    • 2006
  • Recently the electrostatic 2-axis MEMS stages have been fabricated f3r the purpose of an application to PSD (Probe-based Storage Device). However, all of the components (platform, comb electrodes, springs, anchors, etc.) in those stages are placed in-plane so that they have low areal efficiencies such as a few percentage, which is undesirable as data storage devices. In this paper, we present a novel structure of an electrostatic 2-axis MEMS stage that is characterized by having a large areal efficiency of about 25%. For obtaining large area efficiency, the actuator part consisting of mainly comb electrodes and springs is placed right below the platform. The structure and operational principle of the MEMS stage are described, followed by a design and analysis, the fabrication and measurement results. Experimental results show that the driving ranges of the fabricated stage along the x and y axis were 27$\mu$m, 38$\mu$m at the supplied voltages of 65V, 70V, respectively and the natural frequencies along x and y axis were 180Hz, 310Hz, respectively. The total size of the stage is about 5.9$\times$6.8mm$^2$ and the platform size is about 2.7$\times$3.6mm$^2$.

패키징으로 인한 응력이 MEMS 소자에 미치는 영향 분석 및 개선 (Effects of Package Induced Stress on MEMS Device and Its Improvements)

  • 좌성훈;조용철;이문철
    • 한국정밀공학회지
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    • 제22권11호
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    • pp.165-172
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    • 2005
  • In MEMS (Micro-Electro-Mechanical System), packaging induced stress or stress induced structure deformation becomes increasing concerns since it directly affects the performance of the device. In the decoupled vibratory MEMS gyroscope, the main factor that determines the yield rate is the frequency difference between the sensing and driving modes. The gyroscope, packaged using the anodic bonding at the wafer level and EMC (epoxy molding compound) molding, has a deformation of MEMS structure caused by thermal expansion mismatch. This effect results in large distribution in the frequency difference, and thereby a lower yield rate. To improve the yield rate we propose a packaged SiOG (Silicon On Glass) process technology. It uses a silicon wafer and two glass wafers to minimize the wafer warpage. Thus the warpage of the wafer is greatly reduced and the frequency difference is more uniformly distributed. In addition. in order to increase robustness of the structure against deformation caused by EMC molding, a 'crab-leg' type spring is replaced with a semi-folded spring. The results show that the frequency shift is greatly reduced after applying the semi-folded spring. Therefore we can achieve a more robust vibratory MEMS gyroscope with a higher yield rate.

Fabrication of Micro-inductor and Capacior For RF MEMS Applications

  • Cho, Bek-Hee;Lee, Jae-Ho;Bae, Young-Ho;Cho, Chan-Sub;Lee, Jong-Hyun
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제2권2호
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    • pp.102-110
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    • 2002
  • In this paper, we present the fabrication of tunable capacitors and 3-dimensional inductors. This work was related to fabricated 3-dimensional device for need of micro device in developing new intelligence age. This device was fabricated by electroplating used electroplating PR and high-vacuum evaporation of metal. Fabricated micro-inductor is consisted of air-bridge on electroplating rod and electroplated core. Micro-capacitor is consisted of thin metal membrane and electroplated core. Electroplating material is used Cu metal solvent. Air-gap between metal-layers function as almost perfect isolation layer. The most advantage of our micro-inductor and micro-capacitor compared to present device is a possibility that can fabricate on RF MEMS(microelectro-mechanical systems) application with high performance and various function. In this paper, we present the fabrication of tunable capacitors and 3-dimensional inductors. This work was related to fabricated 3-dimensional device for need of micro-device in developing new intelligence age. This device was fabricated by electroplating used electroplating PR and high-vacuum evaporation of metal. Fabricated micro-inductor is consisted of air-bridge on electroplating rod and electroplated core. Micro-capacitor is consisted of thin metal membrane and electroplated core. Electroplating material is used Cu metal solvent. Air-gap between metal-layers function as almost perfect isolation layer. The most advantage of our micro-inductor and micro-capacitor compared to present device is a possibility that can fabricate on RF MEMS application with high performance and various functions.

수평 구동형 MEMS 관성 스위치 설계 및 성능해석 (Design and Performance Analysis of Lateral Type MEMS Inertial Switch)

  • 김학성;장승교
    • 한국항공우주학회지
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    • 제48권7호
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    • pp.523-528
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    • 2020
  • 스프링-메스 시스템의 원리를 이용하여 수평 구동형 MEMS 관성 스위치를 설계하였다. 본 MEMS 스위치는 외부에서 발생하는 가속도를 감지하여 점화안전장치를 장전시키는 역할을 한다. 성능 모델링을 통하여 다양한 가속도 조건에서의 구동 양상을 분석하였다. 시뮬레이션 결과 가속도의 기울기가 10g/msec 이하인 경우에 MEMS 스위치는 10g에서 잘 작동하는 것으로 나타났다. 반면에, 설계 변수들의 공차를 10%로 고려한 시뮬레이션 결과 스프링 폭과 길이에 의해 임계 동작 가속도가 규격(10±2g)을 벗어났다. 제작 공정상 10% 이하의 공차 관리가 어려운 스프링 폭을 두 배로 늘렸을 때 규격을 만족하는 것을 확인하고 설계보완을 제안하였다.

유리 기판과 패인 홈 모양의 홀을 갖는 웨이퍼를 이용한 웨이퍼 레벨 패키지 (Wafer Level Package Using Glass Cap and Wafer with Groove-Shaped Via)

  • 이주호;박해석;신제식;권종오;신광재;송인상;이상훈
    • 전기학회논문지
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    • 제56권12호
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    • pp.2217-2220
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    • 2007
  • In this paper, we propose a new wafer level package (WLP) for the RF MEMS applications. The Film Bulk Acoustic Resonator (FBAR) are fabricated and hermetically packaged in a new wafer level packaging process. With the use of Au-Sn eutectic bonding method, we bonded glass cap and FBAR device wafer which has groove-shaped via formed in the backside. The device wafer includes a electrical bonding pad and groove-shaped via for connecting to the external bonding pad on the device wafer backside and a peripheral pad placed around the perimeter of the device for bonding the glass wafer and device wafer. The glass cap prevents the device from being exposed and ensures excellent mechanical and environmental protection. The frequency characteristics show that the change of bandwidth and frequency shift before and after bonding is less than 0.5 MHz. Two packaged devices, Tx and Rx filters, are attached to a printed circuit board, wire bonded, and encapsulated in plastic to form the duplexer. We have designed and built a low-cost, high performance, duplexer based on the FBARs and presented the results of performance and reliability test.

Advances in MEMS Based Planar VOA

  • Lee, Cheng-Kuo;Huang, RueyShing
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제7권3호
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    • pp.183-195
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    • 2007
  • MEMS technology is proven to be an enabling technology to realize many components for optical networking applications. Due to its widespread applications, VOA has been one of the most attractive MEMS based key devices in optical communication market. Micromachined shutters and refractive mirrors on top of silicon substrate or on the device layer of SOI (Silicon-on-insulator) substrate are the approaches trapped tremendous research activities, because such approaches enable easier alignment and assembly works. These groups of devices are known as the planar VOAs, or two-dimensional (2-D) VOAs. In this review article, we conduct the comprehensively literature survey with respect to MEMS based planar VOA devices. Apparently MEMS VOA technology is still evolving into a mature technology. MEMS VOA technology is not only the cornerstone to support the future optical communication technology, but the best example for understanding the evolution of optical MEMS technology.

MEMS CMP에서 모니터링 시스템을 이용한 슬러리 특성 (The Surry Characteristic Using Monitoring System in MEMS CMP)

  • 박성민;정석훈;박범영;이상직;정원덕;장원문;정해도
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.573-574
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    • 2006
  • The planarization technology of Chemical-mechanical polishing(CMP), used for the manufacturing of multi-layer various material interconnects for Large-scale Integrated Circuits (LSI), is also readily adaptable as an enabling technology in MicroElectroMechanical System (MEMS) fabrication, particularly polysilicon surface micromachining. However, general LSI device CMP has partly distinction aspects, the pattern scale and material sorts in comparison with MEMS CMP. This study performed preliminary CMP tests to identify slurry characteristic used in general IC device. The experiment result is possible to verify slurry characteristic in MEMS structure material.

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MEMS 공정을 이용한 32x32 실리콘 캔틸레버 어레이 제작 및 특성 평가 (Fabrication and Characterization of 32x32 Silicon Cantilever Array using MEMS Process)

  • 김영식;나기열;신윤수;박근형;김영석
    • 한국전기전자재료학회논문지
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    • 제19권10호
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    • pp.894-900
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    • 2006
  • This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.