• International journal of advanced smart convergence
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• v.11 no.1
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• pp.28-35
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• 2022

This paper presents a performance evaluation of real-time Linux for industrial real-time platforms. On industrial platforms, multicore processors are popular due to their work distribution efficiency and cost-effectiveness. Multicore processors, however, are not designed for applications with real-time constraints, and their performance capabilities depend on their core configurations. In order to assess the feasibility of a multicore processor for real-time applications, we conduct a performance evaluation of a general processor and a low-power processor to provide an experimental environment of real-time Linux on both Xenomai and RT-preempt considering the multicore configuration. The real-time performance is evaluated through scheduling latency and in an environment with loads on the CPU, memory, and network to consider an actual situation. The results show a difference between a low-power and a general-purpose processor, but from developer's point of view, it shows that the low-power processor is a proper solution to accommodate low power situations.

• Journal of Korea Society of Digital Industry and Information Management
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• v.4 no.1
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• pp.9-16
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• 2008

This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.71-77
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• 2015

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.37-42
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• 2016

While datacenter operation cost increases with electricity price rise, many researchers study low-power processor based supercomputers to reduce power consumption of datacenters. Reliability of low-power processors for supercomputers can be of concern since the reliability of many low-power processors are assessed based on mobile use conditions. This paper assessed the reliability of low-power processor packages based on supercomputer use conditions. Temperature cycling was determined as a critical failure cause of low-power processor packages through literature surveys and failure mode, effect and criticality analysis. The package temperature was measured at multiple processor load conditions to examine the relationship between processor load and package temperature. A physics-of-failure reliability model associated with temperature cycling predicted the expected lifetime of low-power processors to be less than 3 years. Recommendations to improve the lifetime of low-power processors were presented based on the experimental results.

• ETRI Journal
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• v.37 no.1
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• pp.107-117
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• 2015

This paper presents an energy-efficient (low power) prime-field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a $0.13{\mu}m$ standard CMOS technology, performs an 81-bit divisor multiplication in 503 ms consuming only $6.55{\mu}J$ of energy (average power consumption is $12.76{\mu}W$). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.940-948
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• 2008

This paper presents a low-power, low-complexity design and implementation results of a high speed multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor is composed of the physical layer convergence procedure (PLCP) processor and physical medium dependent (PMD) processor, which have been optimized to have low-power and reduced-complexity architecture. It was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. As a result, the proposed TX-PLCP processor reduced the power consumption by as much as 81% over the bit-level operation architecture. Also, the proposed MIMO symbol detector reduced the hardware complexity by 18% over the conventional SQRD-based architecture with division circuits and square root operations.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• ETRI Journal
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• v.26 no.6
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• pp.513-519
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• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• Journal of the Korea Institute of Military Science and Technology
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• v.8 no.2 s.21
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• pp.30-37
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• 2005

In this paper, we propose how to design a fire control system main control board for individual combat weapons using a small and low power processor. To design an electric board of small weapon systems, Size and power consumption are very important factors. We solved the problem using selection of an adaptive processor, introduction of MicroChipPackaging method, and separate design of a main board Also we applied these methods to make the fire control system for small arms.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.321-324
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• 2001

This paper describes a fast and low-power multiplier co-processor architecture for digital signal processing applications and real-time control systems and its use as a multiplier co-processor for a 32-bit RISC microprocessor utilizing its one of the 16 co-processor interfaces. Its architecture adopts various algorithms to reduce the dynamic power and the area as well. The designed multiplier performs 32$\times$32 bit multiplication, and was designed using verilog HDL and 0.35${\mu}{\textrm}{m}$, 3V, 4M CMOS standard cell library. Its target operating speed is 40MHz, area lower than 10000 gate counts, and 10mW/MHz of power.