IEIE Transactions on Smart Processing and Computing

The Institute of Electronics and Information Engineers (대한전자공학회)
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80μW/MHz 0.68V Ultra Low-Power Variation-Tolerant Superscalar Dual-Core Application Processor

  • Kwon, Youngsu (SoC Research Department, Electronics and Telecommunications Research Institute (ETRI)) ;
  • Lee, Jae-Jin (SoC Research Department, Electronics and Telecommunications Research Institute (ETRI)) ;
  • Shin, Kyoung-Seon (SoC Research Department, Electronics and Telecommunications Research Institute (ETRI)) ;
  • Han, Jin-Ho (SoC Research Department, Electronics and Telecommunications Research Institute (ETRI)) ;
  • Byun, Kyung-Jin (SoC Research Department, Electronics and Telecommunications Research Institute (ETRI)) ;
  • Eum, Nak-Woong (SoC Research Department, Electronics and Telecommunications Research Institute (ETRI))
  • Received : 2014.11.20
  • Accepted : 2015.02.12
  • Published : 2015.04.30
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Abstract

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

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References

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