• Journal of Power Electronics
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• v.17 no.5
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• pp.1186-1194
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• 2017

This paper proposes an improved low frequency Selective Harmonic Mitigation-PWM (SHM-PWM) technique. The proposed method mitigates the low order harmonics of the output voltage up to the $50^{th}$ harmonic well and satisfies the grid codes EN 50160 and CIGRE-WG 36-05. Using a modified criterion for the switching angles, the range of the modulation index for non-linear SHM equations is improved, without increasing the switching frequency of the CHB converter. Due to the low switching frequency of the CHB converter, mitigating the harmonics of the converter up to the $50^{th}$ order and finding a wider modulation index range, the size and cost of the passive filters can be significantly reduced with the proposed technique. Therefore, the proposed technique is more efficient than the conventional SHM-PWM. To verify the effectiveness of the proposed method, a 7-level Cascaded H-bridge (CHB) converter is utilized for the study. Simulation and experimental results confirm the validity of the above claims.

• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• Journal of Electrical Engineering and Technology
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• v.1 no.1
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• pp.63-72
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• 2006

The purpose of this raper is to address the negative impedance instability in DC/DC converters. We present the negative impedance instability of PWM DC/DC converters loaded by constant power loads (CPLs). An approach to design digital controllers for DC/DC converters Is presented. The proposed method, called Power Alignment control technique, is applied to DC/DC step-down choppers operating in continuous conduction or discontinuous conduction modes with CPLs. This approach uses two predefined state variables instead of conventional pulse width modulation (PWM) to regulate the output voltage. A comparator compares actual output voltage with the reference and then switches between the appropriate states. It needs few logic gates and comparators to be implemented thus, making it extremely simple and easy to develop using a low-cost application specific integrated circuit (ASIC) for converters with CPLs. Furthermore, stability of the proposed controllers using the small signal analysis as well as the second theorem of Lyapunov is verified. Finally, simulation and analytical results are presented to describe and verify the proposed technique.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.425-428
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• 2017

This paper describes a full-wave rectifiers for energy harvesting circuit using a vibrational energy. The designed circuit is applied to the negative voltage converter with the body-bias technique using the Beta-multiplier so that the power efficiency is excellent even at the low voltage, and the comparator is designed as the bulk-driven type. The proposed circuit is designed with $0.35{\mu}m$ CMOS process, and The designed chip occupies $931{\mu}m{\times}785{\mu}m$.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.123-131
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• 1997

Design of single stage AC/DC converter with high power factor for low power level applications is proposed. The proposed converter gives the good power factor correction, low line current harmonic distortions, and tight output voltage regulations. This converter also has a high efficiency by employing an active clamp method and synchronous rectifiers. To verify the performances of the proposed converter, a 90W-converter has been designed. The modelling of this proposed converter is power formed using an averaging technique and based on this model a detailed analysis is carried out. This prototype meets the IEC555-2 requirements satisfactorily with nearly unity power factor and high efficiency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1407-1413
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• 2000

This paper presents a feedforward linear power amplifier (LPA) using error feedback technique to achieve low intermodulation distortions(IMD) of power amplifiers for base stations. Especially, the proposed linear power amplifier is applied to feedforward technique combined with error feedback technique, which has no loss of amplifier gain unlike typical feedback technique. The proposed LPA is designed by using HP ADS ver. 1.3, fabricated. When two-tone signals at 1850 MHz and 1851.25 MHz with -7 dBm/tone from synthesizers are injected into the main power amplifier with gain of 28 dB and P1dB of 1W, the proposed LPA could reduce more than 35 dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.12 s.354
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• pp.9-15
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• 2006

In this paper, signal processing techniques for noncoherent impulse-radio-based UWB (IR-UWB) communication system are proposed to provide system implementation of low power consumption and low complexity. The proposed system adopts a simple modulation technique of OOK (on-oft-keying) and noncoherent signal detection based on signal amplitude. In particular, a technique of a novel high speed digital sampler using a stable, lower reference clock is developed to detect nano-second pulses and recover digital signals from the pulses. Also, a 32 bits Turyn code for data frame synchronization and a convolution code as FEC are applied, respectively. To verify the proposed signal processing techniques for low power, low complexity noncoherent IR-UWB system, the proposed signal processing technique is implemented in FPGA and then a short-range communication system for wireless transmission of high quality MP3 data is designed and tested.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.71-74
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• 2002

We have development the dimming controller using the ac chopper technique. The ac chopper change the amplitude of the input source voltage with the unchanged its frequency. The conventional dimming controller is operated by controlling voltage phase and is consist of the triac. It has a bad characteristic about a current THD and a power factor. But the dimming controller using the at chopper technique has a low current THD and a good power factor. The developed dimming controller is consist of the MOSFET and the low pass filter. The system is operated by the variation circuit of the input source voltage and the microprocessor.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.4
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• pp.177-182
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• 2003

We have proposed the dimming controller using the AC chopper technique. The AC chopper changes the amplitude of the input source voltage with the same frequency. The conventional dimming controller is operated by controlling voltage phase with the triac. It has bad characteristics of the input current THD and the input power factor But the dimming controller using the ac chopper technique has a low current THD and a good power factor. The developed dimming controller is consist of the IGBT and the low pass filter. The system is operated by the variation circuit of the input source voltage and the microprocessor.