• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
• /
• pp.163-165
• /
• 2003

Over the past several years, the application extent of the real-time systems is being expanded with the progress of civilization. An effort to minimize power consumption at the system is being accomplished in several fields from the design of an analog/digital circuit up to the device level Things of this effort have included the power optimum-technique to minimize power consumption at the digital logic circuit and the dynamic managed skill by means o( the decision of the operating system. In this paper, we designed of low power system by using Power-optimized method. As an effective low-power design, we designed the low power system which it has a monitoring system within the main board and a personal computer.

• 전기학회논문지P
• /
• 제62권3호
• /
• pp.145-150
• /
• 2013

A novel AC to DC PWM converters with unity input power factor are proposed to overcome the above shortcoming. The main function of these converters is to shape the input line current to force it exactly in phase with the input AC voltage. Therefore, the input power factor can be improved to near unity and the input current harmonics can be eliminated. In this paper, half-bridge converter with two active switches and two diodes are utilized for low-cost type UPS configuration. By having only two semiconductors in the current path at any time, losses can be reduced over the conventional boost topology. Also, this converter provides controllable dc-link voltage, high power factor, and low cost type converter by simple power circuits. Simulation results show that the proposed half-bridge converter/inverter control technique can be applied to single-phase low-cost type UPS systems successfully.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2000년도 전력전자학술대회 논문집
• /
• pp.305-308
• /
• 2000

A technique to suppress the low frequency ripple voltage of the DC output in three phase buck diode rectifiers is presented in this paper. The proposed pulse frequency modulation methods and duty ratio modulation methods are employed to regulate the output voltage of the buck diode rectifiers and guarantee zero-current -switching(ZCS) of the switch over the wide load range The proposed control methods used in this paper provide generally good performance such as low THD of the input line current and unity power factor. IN addition control methods can be effectively used to suppress the low frequency ripple voltage appeared in the dc output voltage. The harmonic injection technique illustrates its validity and effectiveness through the simulations.

• 전자공학회논문지C
• /
• 제34C권12호
• /
• pp.28-36
• /
• 1997

In this paper, system application techniques of a low-voltage low-power CMOS comparator are proposed. The proposed techniques employ poly-layer lines instead of conventional dummy cells to improve the accuracy of comparators which are located in both ends of a comparator array. This technique is easily applicable for hihg-density systems such as memory. The proposed circuits are implemented using a 0.6 um signle-poly double-metal n-well CMOS technology and the dissipated power is 0.38 mW. at a 20MHz clock speed based on a 3V supply. The comparator offsets are measured separately and compared for system applications. Using the proposed techniues, the measured comparator offsets are reduced by 40% of a conventional case.

• 융합신호처리학회논문지
• /
• 제15권4호
• /
• pp.141-147
• /
• 2014

웨이블릿 축소기법은 웨이블릿 변환 계수의 분산 값에 의해 결정되는 경계값을 이용해서 원신호와 잡음신호 간의 MSE(Mean Square Error)가 최소가 되도록 웨이블릿 변환된 계수를 축소하는 방법이다. 이 논문에서는 단조변환 및 웨이블릿 서브밴드의 전력을 이용해서 고주파 및 저주파 웨이블릿 밴드에 적용되는 새로운 경계값들을 제시하고, 이 값들과 ST(soft-threshold) 연산자에 의해 영상신호에 부가된 가우시안 잡음을 제거하였다. 그리고 그 결과를 VisuShrink방법 및 [15]에서의 제시한 기법의 결과와 PSNR로 비교, 평가하고 이 기법의 실용성을 밝혔다.

• 정보처리학회논문지A
• /
• 제14A권3호
• /
• pp.147-150
• /
• 2007

본 논문에서는 작은 점유면적과 저 전력 소모 특성을 갖도록 CPL(Complementary Pass-Transistor Logic) 논리구조의 전가산기에 저 전압 스윙 기술을 적용하여 16$\times$16 비트 병렬 곱셈기를 설계하였다. 회로구성상 CPL 논리구조는 CMOS 논리구조에 비해 NMOS 트랜지스터만을 사용하기 때문에 작은 면적을 소비한다. 저 전압 스윙 기술은 회로에 공급되는 전압보다 낮은 전압 레벨에서 출력 동작을 하여 전력 소모를 감소시키는 기술이다. 본 논문에서는 전가산기의 출력 단에 사용되는 인버터에 저 전압 스윙 기술을 적용하여 저 전력 소모 특성을 갖는 16$\times$16 비트 병렬 곱셈기를 설계하였다 설계한 회로는 17.3%의 전력 소모 감소와 16.5%의 전력소모와 지연시간의 곱(Power Delay) 감소가 이루어졌다.

• 대한전자공학회논문지SD
• /
• 제42권2호
• /
• pp.41-48
• /
• 2005

본 논문은 기존의 CVSL 전가산기 회로 내부에 Low-Swing 기술의 특성을 갖도록 NMOS 트랜지스터를 추가하여 감소된 출력전압으로 동작하는 CVSL 전가산기를 제안하였다. 또한 제안한 Low-Swing CVSL 전가산기를 이용하여 $8\times8$ 병렬 곱셈기를 구성한 후 회로의 성능을 평가하였다. 본 논문에서 제안한 Low-Swing CVSL 전가산기 회로는 $13.1\%$의 전력감소와 $14.3\%$의 전력소모와 지연시간의 곱(power-delay-product) 감소가 이루어졌다 Hynix $0.35{\mu}m$ 표준 CMOS 공정을 사용하여 HSPICE로 시뮬레이션하고 그 동작 특성을 검증하였다.

• Journal of electromagnetic engineering and science
• /
• 제15권2호
• /
• pp.82-88
• /
• 2015

The magnetron, a vacuum tube, is currently the usual high-power microwave power source used for microwave heating. However, the oscillating frequency and output power are unstable and noisy due to the low quality of the high-voltage power supply and low Q of the oscillation circuit. A heating system with enhanced reliability and the capability for control of chemical reactions is desired, because microwave absorption efficiency differs greatly depending on the object being heated. Recent studies on microwave high-efficiency power amplifiers have used harmonic processing techniques, such as class-F and inverse class-F. The present study describes a high-efficiency 100 W GaN-HEMT amplifier that uses a harmonic processing technique that shapes the current and voltage waveforms to improve efficiency. The fabricated GaN power amplifier obtained an output power of 50.4 dBm, a drain efficiency of 72.9%, and a power added efficiency (PAE) of 64.0% at 2.45 GHz for continuous wave operation. A prototype microwave heating system was also developed using this GaN power amplifier. Microwaves totaling 400 W are fed from patch antennas mounted on the top and bottom of the microwave chamber. Preliminary heating experiments with this system have just been initiated.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
• /
• pp.87-90
• /
• 2002

This paper describes design technique of switched-capacitor 1V delta-sigma modulator. To solve the incomplete switching operation at low voltage, bootstrapping technique is used. For PMOS input pair of 1V operational amplifier, simple common mode level down technique is used. Designed 2nd order single loop modulator has an oversampling ratio of 64 and obtains a peak SNR of 71dB, a dynamic range of 73 dB with the power consumption of 350uW at 1V power supply.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
• /
• pp.428-430
• /
• 2006

This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.