• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.4
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• pp.177-177
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• 2003

We have proposed the dimming controller using the AC chopper technique. The AC chopper changes the amplitude of the input source voltage with the same frequency. The conventional dimming controller is operated by controlling voltage phase with the triac. It has bad characteristics of the input current THD and the input power factor But the dimming controller using the ac chopper technique has a low current THD and a good power factor. The developed dimming controller is consist of the IGBT and the low pass filter. The system is operated by the variation circuit of the input source voltage and the microprocessor.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1217-1220
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• 2003

A low-power design technique for lithium-ion Battery-Protection Integrated Circuit (BPIC) for multi cell configuration is proposed. The hardware sharing scheme with more precisely divided operating states in the detection range could reduce the power consumption significantly, especially during the normal state. The usefulness of the proposed scheme was confirmed through HSPICE simulations.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1018-1019
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• 2015

Recently, standby power reduction techniques of AC/DC adaptor were developed, consuming power almost arrived to 300mW level. The standby power losses are composed of the input filter loss 11.8mW, the control IC for AC/DC adaptor 18mW, the switching loss 9.53mW and the feedback loss 123mW. And there are the standby power reduction techniques. In this paper, in order to reduce the standby power of SMPS more, the loss due to a voltage difference between input and output is reduced by the control circuit which is composed of the low voltage driving circuit and voltage regulator. The low voltage driving circuit operates on the low voltage of input and off the high voltage. The low voltage driving IC was produced by the $1.0{\mu}m$, high voltage DMOS process.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1234-1238
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• 2005

As the low power GPS signal is susceptible to interference, interference can seriously degrade the performance of GPS receiver. This paper designs a ANIEF(Adaptive Narrowband Interference Excision in Frequency domain) filter that removes narrow band interferences with low signal loss. This filter uses the pre-correlation technique and attempts to filter out the interference in the frequency domain. The interference excision performance of the designed filter is evaluated for various interferences using the ANIEF filter inserted GPS software receiver and the interference generator. Interferences considered in this paper are single-tone CWI(Continuous Wave Interference), multi-tones CWI, pulsed CWI, and swept CWI. The narrowband interference excision filter in frequency domain is very effective against various interferences and the strong interference with a simple structure. However, the signal power loss is unavoidable while transforming. In this paper, the hamming window and overlap technique are adopted to reduce the signal power loss. Finally, the interference excision performance and the reduced signal power loss of the ANIEF filter are shown.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.2
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• pp.124-130
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• 2005

In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.1-6
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• 2006

In this paper, a RTL binding technique and low power technology mapping consider CPLD is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD consider low power. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in the power consumption by 43% comparing with that of non application algorithm.

• Journal of Power Electronics
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• v.19 no.2
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• pp.413-430
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• 2019

This paper presents an optimum hybrid SVPWM technique for three-level voltage source inverters (VSIs). The proposed hybrid SVPWM technique aims to minimize total harmonic distortion (THD). A new parameter is introduced to incorporate the heterogeneous nature of switching sequences of SVPWM technique. The proposed hybrid SVPWM technique is implemented on a low-cost PIC microcontroller (PIC18F452) and verified experimentally with a 2 KVA three-phase three-level insulated gate bipolar transistor-based VSI. Optimum switching sequence results in the three-level inverter configuration are demonstrated. The proposed hybrid SVPWM technique improves the THD performance by 17.3% compared with the best available three-level SVPWM technique.

• Journal of Power Electronics
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• v.18 no.2
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• pp.573-587
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• 2018

Recently evolved power electronics' based domestic/residential appliances have begun to behave as single phase non-linear loads. Performing as voltage/current harmonic sources, those loads when connected to a three phase distribution network contaminate the line current with harmonics in addition to creating a neutral wire current increase. In this paper, an enhanced performance three phase four leg shunt active power filter (SAPF) controller is presented as a solution for this problem. The presented control strategy incorporates a hybrid predictive fuzzy-logic based technique. The predictive part is responsible for the SAPF compensating current generation while the DC-link voltage control is performed by a fuzzy logic technique. Simulations at various loading conditions are carried out to validate the effectiveness of the proposed technique. In addition, an experimental test rig is implemented for practical validation of the of the enhanced performance of the proposed technique.

• ETRI Journal
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• v.32 no.2
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• pp.327-329
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• 2010

A fully integrated small form-factor HBT power amplifier (PA) was developed for UMTS Tx applications. For practical use, the PA was implemented with a well configured bottom dimension, and a CMOS control IC was added to enable/disable the HBT PA. By using helix-on-pad integrated passive device output matching, a chip-stacking technique in the assembly of the CMOS IC, and embedding of the bulky inductive lines in a multilayer substrate, the module size was greatly reduced to 2 mm ${\times}$ 2.2 mm. A stage-bypass technique was used to enhance the efficiency of the PA. The PA showed a low idle current of about 20 mA and a PAE of about15% at an output power of 16 dBm, while showing good linearity over the entire operating power range.

• Journal of Power Electronics
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• v.5 no.1
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• pp.11-19
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• 2005

This paper describes the two control techniques to perform the sensorless vector control of a PMSM by injecting the high frequency voltage to the stator terminal. The first technique is the estimation algorithm of the initial rotor position. A PMSM possesses the saliency which produces the ellipse of the stator current when the high frequency voltage is injected into the motor terminal. The major axis angle of the current ellipse gives the rotor position information at a standstill. The second control technique is a sensorless control algorithm that injects the high frequency voltage to the stator terminal in order to estimate the rotor position and speed. The rotor position and speed for sensorless vector control is calculated by appropriate signal processing to extract the position information from the stator current at low speeds or standstill. The proposed sensorless algorithm using the double-band hysteresis controller exhibits excellent reference tracking and increased robustness. Experimental results are presented to verify the feasibility of the proposed control schemes. Speed, position estimation and vector control were carried out on the floating point processor TMS320VC33.