• Title/Summary/Keyword: Low-density parity-check( LDPC) codes

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Performance Of Iterative Decoding Schemes As Various Channel Bit-Densities On The Perpendicular Magnetic Recording Channel (수직자기기록 채널에서 기록 밀도에 따른 반복복호 기법의 성능)

  • Park, Dong-Hyuk;Lee, Jae-Jin
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.7C
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    • pp.611-617
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    • 2010
  • In this paper, we investigate the performances of the serial concatenated convolutional codes (SCCC) and low-density parity-check (LDPC) codes on perpendicular magnetic recording (PMR) channels. We discuss the performance of two systems when user bit-densities are 1.7, 2.0, 2.4 and 2.8, respectively. The SCCC system is less complex than LDPC system. The SCCC system consists of recursive systematic convolutional (RSC) codes encoder/decoder, precoder and random interleaver. The decoding algorithm of the SCCC system is the soft message-passing algorithm and the decoding algorithm of the LDPC system is the log domain sum-product algorithm (SPA). When we apply the iterative decoding between channel detector and the error control codes (ECC) decoder, the SCCC system is compatible with the LDPC system even at the high user bit density.

Low Density Parity Check Codes for Hybrid ARQ System

  • Kim, Woo-Tae;Kim, Jeong-Goo;Joo, Eon-Kyeong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.4C
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    • pp.370-378
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    • 2007
  • The most appropriate low density parity check (LDPC) code for hybrid automatic repeat request (HARQ) system suitable for future multimedia communication systems is presented in this paper. HARQ system with punctured LDPC code is investigated at first. And two transmission schemes with parallel concatenated LDPC code are also presented and their performances are analyzed according to the various values of mean column weight (MCW). As a result, the parallel concatenated LDPC code with the diversity effect of information bit is considered to be more appropriate for HARQ system considering the throughput as well as error performance.

On Combining Chase-2 and Sum-Product Algorithms for LDPC Codes

  • Tong, Sheng;Zheng, Huijuan
    • ETRI Journal
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    • v.34 no.4
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    • pp.629-632
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    • 2012
  • This letter investigates the combination of the Chase-2 and sum-product (SP) algorithms for low-density parity-check (LDPC) codes. A simple modification of the tanh rule for check node update is given, which incorporates test error patterns (TEPs) used in the Chase algorithm into SP decoding of LDPC codes. Moreover, a simple yet effective approach is proposed to construct TEPs for dealing with decoding failures with low-weight syndromes. Simulation results show that the proposed algorithm is effective in improving both the waterfall and error floor performance of LDPC codes.

Build-in Wiretap Channel I with Feedback and LDPC Codes

  • Wen, Hong;Gong, Guang;Ho, Pin-Han
    • Journal of Communications and Networks
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    • v.11 no.6
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    • pp.538-543
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    • 2009
  • A wiretap channel I is one of the channel models that was proved to achieve unconditional security. However, it has been an open problem in realizing such a channel model in a practical network environment. The paper is committed to solve the open problem by introducing a novel approach for building wiretap channel I in which the eavesdropper sees a binary symmetric channel (BSC) with error probability p while themain channel is error free. By taking advantage of the feedback and low density parity check (LDPC) codes, our scheme adds randomness to the feedback signals from the destination for keeping an eavesdropper ignorant; on the other hand, redundancy is added and encoded by the LDPC codes such that a legitimate receiver can correctly receive and decode the signals. With the proposed approach, unconditionallysecure communication can be achieved through interactive communications, in which the legitimate partner can realize the secret information transmission without a pre-shared secret key even if the eavesdropper has better channel from the beginning.

Architecture of an LDPC Decoder for DVB-S2 using reuse Technique of processing units and Memory Relocation (연산기와 메모리 재사용을 이용한 효율적인 DVB-S2 규격의 LDPC 복호기 구조)

  • Park Jae-Geun;Lee Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.9 s.351
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    • pp.31-37
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    • 2006
  • Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

An Efficient Overlapped LDPC Decoder with a Upper Dual-diagonal Structure

  • Byun, Yong Ki;Park, Jong Kang;Kwon, Soongyu;Kim, Jong Tae
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.1
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    • pp.8-14
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    • 2013
  • A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

Construction of Structured q-ary LDPC Codes over Small Fields Using Sliding-Window Method

  • Chen, Haiqiang;Liu, Yunyi;Qin, Tuanfa;Yao, Haitao;Tang, Qiuling
    • Journal of Communications and Networks
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    • v.16 no.5
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    • pp.479-484
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    • 2014
  • In this paper, we consider the construction of cyclic and quasi-cyclic structured q-ary low-density parity-check (LDPC) codes over a designated small field. The construction is performed with a pre-defined sliding-window, which actually executes the regular mapping from original field to the targeted field under certain parameters. Compared to the original codes, the new constructed codes can provide better flexibility in choice of code rate, code length and size of field. The constructed codes over small fields with code length from tenths to hundreds perform well with q-ary sum-product decoding algorithm (QSPA) over the additive white Gaussian noise channel and are comparable to the improved spherepacking bound. These codes may found applications in wireless sensor networks (WSN), where the delay and energy are extremely constrained.

Parallel LDPC Decoder for CMMB on CPU and GPU Using OpenCL (OpenCL을 활용한 CPU와 GPU 에서의 CMMB LDPC 복호기 병렬화)

  • Park, Joo-Yul;Hong, Jung-Hyun;Chung, Ki-Seok
    • IEMEK Journal of Embedded Systems and Applications
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    • v.11 no.6
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    • pp.325-334
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    • 2016
  • Recently, Open Computing Language (OpenCL) has been proposed to provide a framework that supports heterogeneous computing platforms. By using an OpenCL framework, digital communication systems can support various protocols in a unified computing environment to achieve both high portability and high performance. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes for China Multimedia Mobile Broadcasting (CMMB) on a heterogeneous platform. Each step of LDPC decoding has different parallelization characteristics. In this paper, steps suitable for task-level parallelization are executed on the CPU, and steps suitable for data-level parallelization are processed by the GPU. To improve the performance of the proposed OpenCL kernels for LDPC decoding operations, explicit thread scheduling, loop-unrolling, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance by using heterogeneous multi-core processors on a unified computing framework.

Estimation-based Watermarking Algorithm with Low Density Parity Check (LDPC) Codes (LDPC를 이용한 예측 기반 워터마킹 알고리듬)

  • Lim, Jae-Hyuck;Won, Chee-Sun
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.44 no.1
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    • pp.76-84
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    • 2007
  • The goal of this paper is to improve the watermarking performance using the following two methods; watermark estimation and low density parity check (LDPC) codes. For a blind watermark decoding, the power of a host image, which is hundreds times greater than the watermark power, is the main noise source. Therefore, a technique that can reduce the effect of the power of the host image to the detector is required. To this end, we need to estimate watermark from the watermarked image. In this paper, the watermark estimation is done by an adaptive estimation method with the generalized Gaussian distribution modeling of sub-band coefficients in the wavelet domain. Since the watermark capacity as well as the error rate can be improved by adopting optimum decoding principles and error correcting codes (ECC), we employ the LDPC codes for the decoding of the estimated watermark. Also, in LDPC codes, the knowledge about the noise power can improve the error correction capability. Simulation results demonstrate the superior performance of the proposed algorithm comparing to LDPC decoding with other estimation-based watermarking algorithms.

LDPC Decoding by Failed Check Nodes for Serial Concatenated Code

  • Yu, Seog Kun;Joo, Eon Kyeong
    • ETRI Journal
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    • v.37 no.1
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    • pp.54-60
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    • 2015
  • The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.